rename CFG_ macros to CONFIG_SYS

[people/ms/u-boot.git] / board / v38b / v38b.c

diff --git a/board/v38b/v38b.c b/board/v38b/v38b.c
index dede996880124cc2053fc86c01a6b66fb36256ae..d77429549700d95b18df2488d9a8ecbbaff2404e 100644 (file)
--- a/board/v38b/v38b.c
+++ b/board/v38b/v38b.c
@@ -29,7 +29,7 @@
 #include <asm/processor.h>
 
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 static void sdram_start(int hi_addr)
 {
        long hi_addr_bit = hi_addr ? 0x01000000 : 0;
@@ -68,16 +68,16 @@ static void sdram_start(int hi_addr)
        *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
        __asm__ volatile ("sync");
 }
-#endif /* !CFG_RAMBOOT */
+#endif /* !CONFIG_SYS_RAMBOOT */
 
 
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
 {
        ulong dramsize = 0;
        ulong dramsize2 = 0;
        uint svr, pvr;
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
        ulong test1, test2;
 
        /* setup SDRAM chip selects */
@@ -98,9 +98,9 @@ long int initdram(int board_type)
 
        /* find RAM size using SDRAM CS0 only */
        sdram_start(0);
-       test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+       test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
        sdram_start(1);
-       test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+       test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
        if (test1 > test2) {
                sdram_start(0);
                dramsize = test1;
@@ -123,10 +123,10 @@ long int initdram(int board_type)
        /* find RAM size using SDRAM CS1 only */
        if (!dramsize)
                sdram_start(0);
-       test2 = test1 = get_ram_size((long *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
+       test2 = test1 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
        if (!dramsize) {
                sdram_start(1);
-               test2 = get_ram_size((long *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
+               test2 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
        }
        if (test1 > test2) {
                sdram_start(0);
@@ -145,7 +145,7 @@ long int initdram(int board_type)
        else
                *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
 
-#else /* CFG_RAMBOOT */
+#else /* CONFIG_SYS_RAMBOOT */
 
        /* retrieve size of memory connected to SDRAM CS0 */
        dramsize = *(vu_long *) MPC5XXX_SDRAM_CS0CFG & 0xFF;
@@ -161,7 +161,7 @@ long int initdram(int board_type)
        else
                dramsize2 = 0;
 
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
        /*
         * On MPC5200B we need to set the special configuration delay in the
@@ -191,16 +191,8 @@ int checkboard (void)
        return 0;
 }
 
-
-int board_early_init_r(void)
+int board_early_init_f(void)
 {
-       /*
-        * Now, when we are in RAM, enable flash write access for the
-        * detection process.  Note that CS_BOOT cannot be cleared when
-        * executing in flash.
-        */
-       *(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
-
 #ifdef CONFIG_HW_WATCHDOG
        /*
         * Enable and configure the direction (output) of PSC3_9 - watchdog
@@ -210,6 +202,17 @@ int board_early_init_r(void)
        *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9;
        *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9;
 #endif /* CONFIG_HW_WATCHDOG */
+       return 0;
+}
+
+int board_early_init_r(void)
+{
+       /*
+        * Now, when we are in RAM, enable flash write access for the
+        * detection process.  Note that CS_BOOT cannot be cleared when
+        * executing in flash.
+        */
+       *(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
 
        /*
         * Enable GPIO_WKUP_7 to "read the status of the actual power
@@ -221,7 +224,7 @@ int board_early_init_r(void)
 }
 
 
-#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
 void init_ide_reset(void)
 {
        debug("init_ide_reset\n");
@@ -245,7 +248,7 @@ void ide_set_reset(int idereset)
        } else
                *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
 }
-#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
+#endif
 
 
 #ifdef CONFIG_HW_WATCHDOG