CONFIG_SPL_SYS_[DI]CACHE_OFF: add

[thirdparty/u-boot.git] / configs / zynq_dlc20_rev1_0_defconfig

diff --git a/configs/zynq_dlc20_rev1_0_defconfig b/configs/zynq_dlc20_rev1_0_defconfig
index c61010f2899d57a5ad09d6bfc3bf2e374f0e7bbf..f9d2b31aacfafcbdd3738ce6d03374fe8a393830 100644 (file)
--- a/configs/zynq_dlc20_rev1_0_defconfig
+++ b/configs/zynq_dlc20_rev1_0_defconfig
@@ -1,11 +1,12 @@
 CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_SPL=y
 CONFIG_DEBUG_UART_BASE=0xe0001000
 CONFIG_DEBUG_UART_CLOCK=50000000
 CONFIG_IDENT_STRING=" Xilinx Zynq DLC20 Rev1.0"
-CONFIG_SPL_STACK_R_ADDR=0x200000
 CONFIG_DEBUG_UART=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
@@ -51,6 +52,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ZYNQ=y
 CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_PHY_REALTEK=y