FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.

[people/ms/u-boot.git] / cpu / mpc85xx / Makefile

diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile
index adbc585827ab22fe6fdce611e0aef60222955467..d51a6dd79f6cf99544dc22dd1da3f99b3e5661b8 100644 (file)
--- a/cpu/mpc85xx/Makefile
+++ b/cpu/mpc85xx/Makefile
@@ -33,8 +33,17 @@ SOBJS-$(CONFIG_MP) += release.o
 SOBJS  = $(SOBJS-y)
 COBJS-$(CONFIG_MP) += mp.o
 COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
+
+ifneq ($(CONFIG_FSL_DDR3),y)
+ifneq ($(CONFIG_FSL_DDR2),y)
+ifneq ($(CONFIG_FSL_DDR1),y)
+COBJS-y        += spd_sdram.o
+endif
+endif
+endif
+
 COBJS  = traps.o cpu.o cpu_init.o speed.o interrupts.o tlb.o \
-         pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o qe_io.o \
+         pci.o serial_scc.o commproc.o ether_fcc.o qe_io.o \
          $(COBJS-y)
 
 SRCS   := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)