]> git.ipfire.org Git - people/ms/u-boot.git/blobdiff - cpu/mpc8xxx/ddr/main.c
Check DDR interleaving mode
[people/ms/u-boot.git] / cpu / mpc8xxx / ddr / main.c
index 700b8971729f84dccced25b04306bc682d7f59d5..21a16d97e12c5e75ab6dcaf1fef891805a78de2b 100644 (file)
@@ -164,6 +164,24 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo,
        }
        if (j == 2) {
                *memctl_interleaving = 1;
+
+               printf("\nMemory controller interleaving enabled: ");
+
+               switch (pinfo->memctl_opts[0].memctl_interleaving_mode) {
+               case FSL_DDR_CACHE_LINE_INTERLEAVING:
+                       printf("Cache-line interleaving!\n");
+                       break;
+               case FSL_DDR_PAGE_INTERLEAVING:
+                       printf("Page interleaving!\n");
+                       break;
+               case FSL_DDR_BANK_INTERLEAVING:
+                       printf("Bank interleaving!\n");
+                       break;
+               case FSL_DDR_SUPERBANK_INTERLEAVING:
+                       printf("Super bank interleaving\n");
+               default:
+                       break;
+               }
        }
 
        /* Check that all controllers are rank interleaving. */
@@ -175,6 +193,25 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo,
        }
        if (j == 2) {
                *rank_interleaving = 1;
+
+               printf("Bank(chip-select) interleaving enabled: ");
+
+               switch (pinfo->memctl_opts[0].ba_intlv_ctl &
+                                               FSL_DDR_CS0_CS1_CS2_CS3) {
+               case FSL_DDR_CS0_CS1_CS2_CS3:
+                       printf("CS0+CS1+CS2+CS3\n");
+                       break;
+               case FSL_DDR_CS0_CS1:
+                       printf("CS0+CS1\n");
+                       break;
+               case FSL_DDR_CS2_CS3:
+                       printf("CS2+CS3\n");
+                       break;
+               case FSL_DDR_CS0_CS1_AND_CS2_CS3:
+                       printf("CS0+CS1 and CS2+CS3\n");
+               default:
+                       break;
+               }
        }
 
        if (*memctl_interleaving) {