Changed CONFIG_440_xx to CONFIG_440xx for a consistent design (405 and linux)

[u-boot.git] / cpu / ppc4xx / 405gp_pci.c

diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c
index ebbcfd573ac9bfc7518c4d22b9f5747f807844b1..89be137a868e6ae6ff0e223de0e3033b9c0c5285 100644 (file)
--- a/cpu/ppc4xx/405gp_pci.c
+++ b/cpu/ppc4xx/405gp_pci.c
@@ -437,7 +437,7 @@ void pci_440_init (struct pci_controller *hose)
         * The PCI initialization sequence enable bit must be set ... if not abort
         * pci setup since updating the bit requires chip reset.
         *--------------------------------------------------------------------------*/
-#if defined (CONFIG_440_GX) || defined (CONFIG_440_EP) || defined(CONFIG_440_GR)
+#if defined (CONFIG_440GX) || defined (CONFIG_440EP) || defined(CONFIG_440GR)
        mfsdr(sdr_sdstp1,strap);
        if ( (strap & 0x00010000) == 0 ){
                printf("PCI: SDR0_STRP1[PISE] not set.\n");
@@ -495,7 +495,7 @@ void pci_440_init (struct pci_controller *hose)
     out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
 #endif
 
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX)
        out32r( PCIX0_BRDGOPT1, 0x04000060 );               /* PLB Rq pri highest   */
        out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1  */
 #elif defined(PCIX0_BRDGOPT1)
@@ -531,7 +531,7 @@ void pci_440_init (struct pci_controller *hose)
 #ifdef CONFIG_PCI_SCAN_SHOW
        printf("PCI:   Bus Dev VenId DevId Class Int\n");
 #endif
-#if !defined(CONFIG_440_EP) && !defined(CONFIG_440_GR)
+#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
        out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
 #endif
        hose->last_busno = pci_hose_scan(hose);