[PATCH] Add support for the AMCC Katmai (440SPe) eval board

[people/ms/u-boot.git] / cpu / ppc4xx / cpu_init.c

diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c
index b27567fa4d14100e2ae07fe83ee3c394da06c29b..82ae4434b0be9a45900d2abc1a9d2305223ce0ce 100644 (file)
--- a/cpu/ppc4xx/cpu_init.c
+++ b/cpu/ppc4xx/cpu_init.c
@@ -31,9 +31,6 @@
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
-
-#define mtebc(reg, data)  mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
-
 #ifdef CFG_INIT_DCACHE_CS
 # if (CFG_INIT_DCACHE_CS == 0)
 #  define PBxAP pb0ap
@@ -222,17 +219,27 @@ void set_chip_gpio_configuration(gpio_param_s (*gpio_tab)[GPIO_GROUP_MAX][GPIO_M
 void
 cpu_init_f (void)
 {
+#if defined(CONFIG_WATCHDOG)
+       unsigned long val;
+#endif
+
 #if defined(CONFIG_405EP)
        /*
         * GPIO0 setup (select GPIO or alternate function)
         */
-       out32(GPIO0_OSRH, CFG_GPIO0_OSRH);   /* output select */
+#if defined(CFG_GPIO0_OR)
+       out32(GPIO0_OR, CFG_GPIO0_OR);          /* set initial state of output pins     */
+#endif
+#if defined(CFG_GPIO0_ODR)
+       out32(GPIO0_ODR, CFG_GPIO0_ODR);        /* open-drain select                    */
+#endif
+       out32(GPIO0_OSRH, CFG_GPIO0_OSRH);      /* output select                        */
        out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
-       out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */
+       out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H);    /* input select                         */
        out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
-       out32(GPIO0_TSRH, CFG_GPIO0_TSRH);   /* three-state select */
+       out32(GPIO0_TSRH, CFG_GPIO0_TSRH);      /* three-state select                   */
        out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
-       out32(GPIO0_TCR, CFG_GPIO0_TCR);     /* enable output driver for outputs */
+       out32(GPIO0_TCR, CFG_GPIO0_TCR);        /* enable output driver for outputs     */
 
        /*
         * Set EMAC noise filter bits
@@ -306,14 +313,20 @@ cpu_init_f (void)
        mtebc(pb7cr, CFG_EBC_PB7CR);
 #endif
 
-#if defined(CONFIG_WATCHDOG)
-       unsigned long val;
+#if defined (CFG_EBC_CFG)
+       mtebc(EBC0_CFG, CFG_EBC_CFG);
+#endif
 
+#if defined(CONFIG_WATCHDOG)
        val = mfspr(tcr);
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
        val |= 0xb8000000;      /* generate system reset after 1.34 seconds */
 #else
        val |= 0xf0000000;      /* generate system reset after 2.684 seconds */
+#endif
+#if defined(CFG_4xx_RESET_TYPE)
+       val &= ~0x30000000;                     /* clear WRC bits */
+       val |= CFG_4xx_RESET_TYPE << 28;        /* set board specific WRC type */
 #endif
        mtspr(tcr, val);