Merge branch 'master' of git://git.denx.de/u-boot-rockchip

[people/ms/u-boot.git] / doc / README.POST

diff --git a/doc/README.POST b/doc/README.POST
index fba498a3a5548cc1debd1a7356105450e0c07ea5..a9335f4d8b9c7d0e3a30404dabb37b0fc27cb912 100644 (file)
--- a/doc/README.POST
+++ b/doc/README.POST
@@ -5,7 +5,7 @@ This project is to support Power-On-Self-Test (POST) in U-Boot.
 
 1. High-level requirements
 
-The key rquirements for this project are as follows:
+The key requirements for this project are as follows:
 
 1) The project shall develop a flexible framework for implementing
    and running Power-On-Self-Test in U-Boot. This framework shall
@@ -72,7 +72,7 @@ tests. All POST tests will be divided into the following groups:
      This group will contain those tests that do not take much
      time and can be run on the regular basis (e.g. CPU test)
 
-  3) Tests running on in special "slow test more" only
+  3) Tests running in special "slow test mode" only
 
      This group will contain POST tests that consume much time
      and cannot be run regularly (e.g. strong memory test, I2C test)
@@ -92,7 +92,7 @@ Specifically, the following groups will be singled out:
 
   1) Tests running before relocating to RAM
 
-     These tests will run immediatelly after initializing RAM
+     These tests will run immediately after initializing RAM
      as to enable modifying it without taking care of its
      contents. Basically, this group will contain memory tests
      only.
@@ -494,7 +494,7 @@ This test will verify the following ALU instructions:
      This group will contain: b, bl, bc.
 
      The first 2 instructions (b, bl) will be verified by jumping to
-     a fixed address and checking whether control was transfered to
+     a fixed address and checking whether control was transferred to
      that very point. For the bl instruction the value of the link
      register will be checked as well (using mfspr). To verify the bc
      instruction various combinations of the BI/BO fields, the CTR
@@ -659,12 +659,19 @@ not need any modifications for porting them to another board/CPU.
 2.2.2.1. I2C test
 
 For verifying the I2C bus, a full I2C bus scanning will be performed
-using the i2c_probe() routine. If any I2C device is found, the test
-will be considered as passed, otherwise failed. This particular way
-will be used because it provides the most common method of testing.
-For example, using the internal loopback mode of the CPM I2C
-controller for testing would not work on boards where the software
-I2C driver (also known as bit-banged driver) is used.
+using the i2c_probe() routine. If a board defines
+CONFIG_SYS_POST_I2C_ADDRS the I2C test will pass if all devices
+listed in CONFIG_SYS_POST_I2C_ADDRS are found, and no additional
+devices are detected.  If CONFIG_SYS_POST_I2C_ADDRS is not defined
+the test will pass if any I2C device is found.
+
+The CONFIG_SYS_POST_I2C_IGNORES define can be used to list I2C
+devices which may or may not be present when using
+CONFIG_SYS_POST_I2C_ADDRS.  The I2C POST test will pass regardless
+if the devices in CONFIG_SYS_POST_I2C_IGNORES are found or not.
+This is useful in cases when I2C devices are optional (eg on a
+daughtercard that may or may not be present) or not critical
+to board operation.
 
 2.2.2.2. Watchdog timer test
 
@@ -713,7 +720,7 @@ use external loopback for testing. That will need appropriate
 reconfiguration of the physical interface chip.
 
 The test routines for the SCC ethernet tests will be located in
-cpu/mpc8xx/scc.c.
+arch/powerpc/cpu/mpc8xx/scc.c.
 
 2.2.3.2. UART tests (SMC/SCC)
 
@@ -725,7 +732,7 @@ will be transmitted. These tests may be enhanced to make to perform
 test will be executed manually.
 
 The test routine for the SMC/SCC UART tests will be located in
-cpu/mpc8xx/serial.c.
+arch/powerpc/cpu/mpc8xx/serial.c.
 
 2.2.3.3. USB test