move erratum a008336 and a008514 to soc specific file

[people/ms/u-boot.git] / doc / README.x86

diff --git a/doc/README.x86 b/doc/README.x86
index e7dc090e76bd409eb12e0a965aaea1e5a88210cd..1271e5edea3a427debce1ff202eecb6aa7cbc4f2 100644 (file)
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -25,6 +25,8 @@ targets and all Intel boards support running U-Boot 'bare metal'.
 
 As for loading an OS, U-Boot supports directly booting a 32-bit or 64-bit
 Linux kernel as part of a FIT image. It also supports a compressed zImage.
+U-Boot supports loading an x86 VxWorks kernel. Please check README.vxworks
+for more details.
 
 Build Instructions for U-Boot as coreboot payload
 -------------------------------------------------
@@ -188,8 +190,9 @@ Offset   Description         Controlling config
 000000   descriptor.bin      Hard-coded to 0 in ifdtool
 001000   me.bin              Set by the descriptor
 500000   <spare>
+6f0000   MRC cache           CONFIG_ENABLE_MRC_CACHE
 700000   u-boot-dtb.bin      CONFIG_SYS_TEXT_BASE
-790000   vga.bin             CONFIG_X86_OPTION_ROM_ADDR
+790000   vga.bin             CONFIG_VGA_BIOS_ADDR
 7c0000   fsp.bin             CONFIG_FSP_ADDR
 7f8000   <spare>             (depends on size of fsp.bin)
 7fe000   Environment         CONFIG_ENV_OFFSET
@@ -245,10 +248,10 @@ this capability yet. The command is as follows:
 
 # in the coreboot root directory
 $ ./build/util/cbfstool/cbfstool build/coreboot.rom add-flat-binary \
-  -f u-boot-dtb.bin -n fallback/payload -c lzma -l 0x1110000 -e 0x1110015
+  -f u-boot-dtb.bin -n fallback/payload -c lzma -l 0x1110000 -e 0x1110000
 
-Make sure 0x1110000 matches CONFIG_SYS_TEXT_BASE and 0x1110015 matches the
-symbol address of _start (in arch/x86/cpu/start.S).
+Make sure 0x1110000 matches CONFIG_SYS_TEXT_BASE, which is the symbol address
+of _x86boot_start (in arch/x86/cpu/start.S).
 
 If you want to use ELF as the coreboot payload, change U-Boot configuration to
 use CONFIG_OF_EMBED instead of CONFIG_OF_SEPARATE.
@@ -330,9 +333,8 @@ In keeping with the U-Boot philosophy of providing functions to check and
 adjust internal settings, there are several x86-specific commands that may be
 useful:
 
-hob  - Display information about Firmware Support Package (FSP) Hand-off
-        Block. This is only available on platforms which use FSP, mostly
-        Atom.
+fsp  - Display information about Intel Firmware Support Package (FSP).
+        This is only available on platforms which use FSP, mostly Atom.
 iod  - Display I/O memory
 iow  - Write I/O memory
 mtrr - List and set the Memory Type Range Registers (MTRR). These are used to
@@ -654,13 +656,13 @@ Use the device tree for configuration where possible.
 For the microcode you can create a suitable device tree file using the
 microcode tool:
 
-  ./tools/microcode-tool -d microcode.dat create <model>
+  ./tools/microcode-tool -d microcode.dat -m <model> create
 
 or if you only have header files and not the full Intel microcode.dat database:
 
   ./tools/microcode-tool -H BAY_TRAIL_FSP_KIT/Microcode/M0130673322.h \
        -H BAY_TRAIL_FSP_KIT/Microcode/M0130679901.h \
-       create all
+       -m all create
 
 These are written to arch/x86/dts/microcode/ by default.
 
@@ -733,6 +735,30 @@ Example output:
    PCI_BDF(0, 3, 0) INTA PIRQA
 ...
 
+Porting Hints
+-------------
+
+Quark-specific considerations:
+
+To port U-Boot to other boards based on the Intel Quark SoC, a few things need
+to be taken care of. The first important part is the Memory Reference Code (MRC)
+parameters. Quark MRC supports memory-down configuration only. All these MRC
+parameters are supplied via the board device tree. To get started, first copy
+the MRC section of arch/x86/dts/galileo.dts to your board's device tree, then
+change these values by consulting board manuals or your hardware vendor.
+Available MRC parameter values are listed in include/dt-bindings/mrc/quark.h.
+The other tricky part is with PCIe. Quark SoC integrates two PCIe root ports,
+but by default they are held in reset after power on. In U-Boot, PCIe
+initialization is properly handled as per Quark's firmware writer guide.
+In your board support codes, you need provide two routines to aid PCIe
+initialization, which are board_assert_perst() and board_deassert_perst().
+The two routines need implement a board-specific mechanism to assert/deassert
+PCIe PERST# pin. Care must be taken that in those routines that any APIs that
+may trigger PCI enumeration process are strictly forbidden, as any access to
+PCIe root port's configuration registers will cause system hang while it is
+held in reset. For more details, check how they are implemented by the Intel
+Galileo board support codes in board/intel/galileo/galileo.c.
+
 TODO List
 ---------
 - Audio