clk: renesas: Synchronize Gen3 tables with Linux 5.0

[thirdparty/u-boot.git] / drivers / clk / renesas / r8a77990-cpg-mssr.c

diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c
index b3614a1355592d73dc37d13baa975ebd4bde06aa..3168de20f91d61b3adc351e8396e75e3b519975c 100644 (file)
--- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
@@ -1,13 +1,13 @@
-// SPDX-License-Identifier: GPL-2.0+
+// SPDX-License-Identifier: GPL-2.0
 /*
- * Renesas R8A77990 CPG MSSR driver
+ * r8a77990 Clock Pulse Generator / Module Standby and Software Reset
  *
- * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
+ * Copyright (C) 2018 Renesas Electronics Corp.
  *
- * Based on the following driver from Linux kernel:
- * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
+ * Based on r8a7795-cpg-mssr.c
  *
- * Copyright (C) 2016 Glider bvba
+ * Copyright (C) 2015 Glider bvba
+ * Copyright (C) 2015 Renesas Electronics Corp.
  */
 
 #include <common.h>
@@ -43,6 +43,9 @@ enum clk_ids {
        CLK_S2,
        CLK_S3,
        CLK_SDSRC,
+       CLK_RPCSRC,
+       CLK_RINT,
+       CLK_OCO,
 
        /* Module Clocks */
        MOD_CLK_BASE
@@ -70,6 +73,11 @@ static const struct cpg_core_clk r8a77990_core_clks[] = {
        DEF_FIXED(".s2",       CLK_S2,             CLK_PLL1,       4, 1),
        DEF_FIXED(".s3",       CLK_S3,             CLK_PLL1,       6, 1),
        DEF_FIXED(".sdsrc",    CLK_SDSRC,          CLK_PLL1,       2, 1),
+       DEF_FIXED(".rpcsrc",   CLK_RPCSRC,         CLK_PLL1,       2, 1),
+
+       DEF_DIV6_RO(".r",      CLK_RINT,           CLK_EXTAL, CPG_RCKCR, 32),
+
+       DEF_RATE(".oco",       CLK_OCO,            8 * 1000 * 1000),
 
        /* Core Clock Outputs */
        DEF_FIXED("za2",       R8A77990_CLK_ZA2,   CLK_PLL0D24,    1, 1),
@@ -96,13 +104,15 @@ static const struct cpg_core_clk r8a77990_core_clks[] = {
        DEF_GEN3_SD("sd1",     R8A77990_CLK_SD1,   CLK_SDSRC,     0x0078),
        DEF_GEN3_SD("sd3",     R8A77990_CLK_SD3,   CLK_SDSRC,     0x026c),
 
+       DEF_GEN3_RPC("rpc",    R8A77990_CLK_RPC,   CLK_RPCSRC,    0x238),
+
        DEF_FIXED("cl",        R8A77990_CLK_CL,    CLK_PLL1,      48, 1),
        DEF_FIXED("cp",        R8A77990_CLK_CP,    CLK_EXTAL,      2, 1),
        DEF_FIXED("cpex",      R8A77990_CLK_CPEX,  CLK_EXTAL,      4, 1),
-       DEF_FIXED("osc",       R8A77990_CLK_OSC,   CLK_EXTAL,    384, 1),
-       DEF_FIXED("r",         R8A77990_CLK_R,     CLK_EXTAL,   1536, 1),
 
-       DEF_GEN3_PE("s0d6c",   R8A77990_CLK_S0D6C, CLK_S0, 6, CLK_PE, 6),
+       DEF_DIV6_RO("osc",     R8A77990_CLK_OSC,   CLK_EXTAL, CPG_RCKCR,  8),
+
+       DEF_GEN3_PE("s0d6c",   R8A77990_CLK_S0D6C, CLK_S0, 6, CLK_PE, 2),
        DEF_GEN3_PE("s3d1c",   R8A77990_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
        DEF_GEN3_PE("s3d2c",   R8A77990_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
        DEF_GEN3_PE("s3d4c",   R8A77990_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
@@ -110,6 +120,8 @@ static const struct cpg_core_clk r8a77990_core_clks[] = {
        DEF_DIV6P1("canfd",    R8A77990_CLK_CANFD, CLK_PLL0D6, 0x244),
        DEF_DIV6P1("csi0",     R8A77990_CLK_CSI0,  CLK_PLL1D2, 0x00c),
        DEF_DIV6P1("mso",      R8A77990_CLK_MSO,   CLK_PLL1D2, 0x014),
+
+       DEF_GEN3_RCKSEL("r",   R8A77990_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
 };
 
 static const struct mssr_mod_clk r8a77990_mod_clks[] = {
@@ -174,12 +186,10 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] = {
        DEF_MOD("ehci0",                 703,   R8A77990_CLK_S3D4),
        DEF_MOD("hsusb",                 704,   R8A77990_CLK_S3D4),
        DEF_MOD("csi40",                 716,   R8A77990_CLK_CSI0),
-       DEF_MOD("du1",                   723,   R8A77990_CLK_S2D1),
-       DEF_MOD("du0",                   724,   R8A77990_CLK_S2D1),
+       DEF_MOD("du1",                   723,   R8A77990_CLK_S1D1),
+       DEF_MOD("du0",                   724,   R8A77990_CLK_S1D1),
        DEF_MOD("lvds",                  727,   R8A77990_CLK_S2D1),
 
-       DEF_MOD("vin7",                  804,   R8A77990_CLK_S1D2),
-       DEF_MOD("vin6",                  805,   R8A77990_CLK_S1D2),
        DEF_MOD("vin5",                  806,   R8A77990_CLK_S1D2),
        DEF_MOD("vin4",                  807,   R8A77990_CLK_S1D2),
        DEF_MOD("etheravb",              812,   R8A77990_CLK_S3D2),
@@ -194,6 +204,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] = {
        DEF_MOD("can-fd",                914,   R8A77990_CLK_S3D2),
        DEF_MOD("can-if1",               915,   R8A77990_CLK_S3D4),
        DEF_MOD("can-if0",               916,   R8A77990_CLK_S3D4),
+       DEF_MOD("rpc",                   917,   R8A77990_CLK_RPC),
        DEF_MOD("i2c6",                  918,   R8A77990_CLK_S3D2),
        DEF_MOD("i2c5",                  919,   R8A77990_CLK_S3D2),
        DEF_MOD("i2c-dvfs",              926,   R8A77990_CLK_CP),
@@ -203,6 +214,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] = {
        DEF_MOD("i2c1",                  930,   R8A77990_CLK_S3D2),
        DEF_MOD("i2c0",                  931,   R8A77990_CLK_S3D2),
 
+       DEF_MOD("i2c7",                 1003,   R8A77990_CLK_S3D2),
        DEF_MOD("ssi-all",              1005,   R8A77990_CLK_S3D4),
        DEF_MOD("ssi9",                 1006,   MOD_CLK_ID(1005)),
        DEF_MOD("ssi8",                 1007,   MOD_CLK_ID(1005)),
@@ -238,8 +250,8 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] = {
 /*
  * MD19                EXTAL (MHz)     PLL0            PLL1            PLL3
  *--------------------------------------------------------------------
- * 0           48 x 1          x100/4          x100/3          x100/3
- * 1           48 x 1          x100/4          x100/3           x58/3
+ * 0           48 x 1          x100/1          x100/3          x100/3
+ * 1           48 x 1          x100/1          x100/3           x58/3
  */
 #define CPG_PLL_CONFIG_INDEX(md)       (((md) & BIT(19)) >> 19)