clk: renesas: Synchronize Gen3 tables with Linux 5.0

[thirdparty/u-boot.git] / drivers / clk / renesas / renesas-cpg-mssr.h

diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
index bad393878511c88d6343d28f8a96d9dee61e1e77..5b7012d37c633b52f3a83ad70b0cc46c7d6bf19d 100644 (file)
--- a/drivers/clk/renesas/renesas-cpg-mssr.h
+++ b/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -57,6 +57,7 @@ enum clk_types {
        CLK_TYPE_FF,            /* Fixed Factor Clock */
        CLK_TYPE_DIV6P1,        /* DIV6 Clock with 1 parent clock */
        CLK_TYPE_DIV6_RO,       /* DIV6 Clock read only with extra divisor */
+       CLK_TYPE_FR,            /* Fixed Rate Clock */
 
        /* Custom definitions start here */
        CLK_TYPE_CUSTOM,
@@ -75,6 +76,8 @@ enum clk_types {
        DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
 #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div)        \
        DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
+#define DEF_RATE(_name, _id, _rate)    \
+       DEF_TYPE(_name, _id, CLK_TYPE_FR, .mult = _rate)
 
 /*
  * Definitions of Module Clocks