ddr: altera: Zero DM IN delay in scc_mgr_zero_group()

[people/ms/u-boot.git] / drivers / ddr / altera / sequencer.c

diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 2bd01092eedc1476fe2c171e4083aaae6f7f07ed..0321e3b5a77017683c24fd0e9b79b2e76fb6f410 100644 (file)
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -279,7 +279,7 @@ static void scc_mgr_initialize(void)
        for (i = 0; i < 16; i++) {
                debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
                           __func__, __LINE__, i);
-               scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i);
+               scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, i, 0);
        }
 }
 
@@ -303,15 +303,22 @@ static void scc_mgr_set_dqs_en_delay(u32 read_group, u32 delay)
        scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
 }
 
+static void scc_mgr_set_dq_in_delay(u32 dq_in_group, u32 delay)
+{
+       scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
+}
+
 static void scc_mgr_set_dqs_io_in_delay(u32 delay)
 {
        scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs,
                    delay);
 }
 
-static void scc_mgr_set_dq_in_delay(u32 dq_in_group, u32 delay)
+static void scc_mgr_set_dm_in_delay(u32 dm, u32 delay)
 {
-       scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
+       scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET,
+                   rwcfg->mem_dq_per_write_dqs + 1 + dm,
+                   delay);
 }
 
 static void scc_mgr_set_dq_out1_delay(u32 dq_in_group, u32 delay)
@@ -424,7 +431,6 @@ static void scc_mgr_set_dqs_en_delay_all_ranks(u32 read_group,
         */
        scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET,
                              read_group, delay, 1);
-       writel(0, &sdr_scc_mgr->update);
 }
 
 /**
@@ -585,8 +591,11 @@ static void scc_mgr_zero_group(const u32 write_group, const int out_only)
                writel(0xff, &sdr_scc_mgr->dq_ena);
 
                /* Zero all DM config settings. */
-               for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
+               for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
+                       if (!out_only)
+                               scc_mgr_set_dm_in_delay(i, 0);
                        scc_mgr_set_dm_out1_delay(i, 0);
+               }
 
                /* Multicast to all DM enables. */
                writel(0xff, &sdr_scc_mgr->dm_ena);
@@ -1208,7 +1217,6 @@ rw_mgr_mem_calibrate_write_test(const u32 rank_bgn, const u32 write_group,
                           *bit_chk == param->write_correct_mask);
                return *bit_chk == param->write_correct_mask;
        } else {
-               set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
                debug_cond(DLEVEL == 2,
                           "write_test(%u,%u,ONE) : %u != %i => %i\n",
                           write_group, use_dm, *bit_chk, 0, *bit_chk != 0);
@@ -1800,7 +1808,7 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp)
        u32 d, p, i;
        u32 dtaps_per_ptap;
        u32 work_bgn, work_end;
-       u32 found_passing_read, found_failing_read, initial_failing_dtap;
+       u32 found_passing_read, found_failing_read = 0, initial_failing_dtap;
        int ret;
 
        debug("%s:%d %u\n", __func__, __LINE__, grp);
@@ -3247,7 +3255,7 @@ static void mem_skip_calibrate(void)
                         *    (1.25 * iocfg->dll_chain_length - 2)
                         */
                        scc_mgr_set_dqdqs_output_phase(i,
-                                      1.25 * iocfg->dll_chain_length - 2);
+                                      ((125 * iocfg->dll_chain_length) / 100) - 2);
                }
                writel(0xff, &sdr_scc_mgr->dqs_ena);
                writel(0xff, &sdr_scc_mgr->dqs_io_ena);
@@ -3479,6 +3487,7 @@ grp_failed:               /* A group failed, increment the counter. */
 static int run_mem_calibrate(void)
 {
        int pass;
+       u32 ctrl_cfg;
 
        debug("%s:%d\n", __func__, __LINE__);
 
@@ -3486,7 +3495,9 @@ static int run_mem_calibrate(void)
        writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
 
        /* Stop tracking manager. */
-       clrbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
+       ctrl_cfg = readl(&sdr_ctrl->ctrl_cfg);
+       writel(ctrl_cfg & ~SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK,
+              &sdr_ctrl->ctrl_cfg);
 
        phy_mgr_initialize();
        rw_mgr_mem_initialize();
@@ -3507,7 +3518,7 @@ static int run_mem_calibrate(void)
        writel(0x2, &phy_mgr_cfg->mux_sel);
 
        /* Start tracking manager. */
-       setbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
+       writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
 
        return pass;
 }