#include <common.h>
#include <asm/io.h>
#include <asm/arch/sdram.h>
+#include <errno.h>
#include "sequencer.h"
#include "sequencer_auto.h"
#include "sequencer_auto_ac_init.h"
#include "sequencer_auto_inst_init.h"
#include "sequencer_defines.h"
-static void scc_mgr_load_dqs_for_write_group(uint32_t write_group);
-
static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
- (struct socfpga_sdr_rw_load_manager *)(BASE_RW_MGR + 0x800);
+ (struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
- (struct socfpga_sdr_rw_load_jump_manager *)(BASE_RW_MGR + 0xC00);
+ (struct socfpga_sdr_rw_load_jump_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
static struct socfpga_sdr_reg_file *sdr_reg_file =
(struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
(struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
- (struct socfpga_phy_mgr_cmd *)(BASE_PHY_MGR);
+ (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
- (struct socfpga_phy_mgr_cfg *)(BASE_PHY_MGR + 0x4000);
+ (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
static struct socfpga_data_mgr *data_mgr =
- (struct socfpga_data_mgr *)(BASE_DATA_MGR);
+ (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
+
+static struct socfpga_sdr_ctrl *sdr_ctrl =
+ (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
#define DELTA_D 1
-#define MGR_SELECT_MASK 0xf8000
/*
* In order to reduce ROM size, most of the selectable calibration steps are
uint32_t write_group, uint32_t use_dm,
uint32_t all_correct, uint32_t *bit_chk, uint32_t all_ranks);
-static u32 sdr_get_addr(u32 *base)
-{
- u32 addr = (u32)base & MGR_SELECT_MASK;
-
- switch (addr) {
- case BASE_PHY_MGR:
- addr = (((u32)base >> 8) & (1 << 6)) | ((u32)base & 0x3f) |
- SDR_PHYGRP_PHYMGRGRP_ADDRESS;
- break;
- case BASE_RW_MGR:
- addr = ((u32)base & 0x1fff) | SDR_PHYGRP_RWMGRGRP_ADDRESS;
- break;
- case BASE_DATA_MGR:
- addr = ((u32)base & 0x7ff) | SDR_PHYGRP_DATAMGRGRP_ADDRESS;
- break;
- case BASE_SCC_MGR:
- addr = ((u32)base & 0xfff) | SDR_PHYGRP_SCCGRP_ADDRESS;
- break;
- case BASE_REG_FILE:
- addr = ((u32)base & 0x7ff) | SDR_PHYGRP_REGFILEGRP_ADDRESS;
- break;
- case BASE_MMR:
- addr = ((u32)base & 0xfff) | SDR_CTRLGRP_ADDRESS;
- break;
- default:
- return -1;
- }
-
- return addr;
-}
-
static void set_failing_group_stage(uint32_t group, uint32_t stage,
uint32_t substage)
{
}
}
-static void reg_file_set_group(uint32_t set_group)
+static void reg_file_set_group(u16 set_group)
{
- u32 addr = (u32)&sdr_reg_file->cur_stage;
-
- /* Read the current group and stage */
- uint32_t cur_stage_group = readl(SOCFPGA_SDR_ADDRESS + addr);
-
- /* Clear the group */
- cur_stage_group &= 0x0000FFFF;
-
- /* Set the group */
- cur_stage_group |= (set_group << 16);
-
- /* Write the data back */
- writel(cur_stage_group, SOCFPGA_SDR_ADDRESS + addr);
+ clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16);
}
-static void reg_file_set_stage(uint32_t set_stage)
+static void reg_file_set_stage(u8 set_stage)
{
- u32 addr = (u32)&sdr_reg_file->cur_stage;
-
- /* Read the current group and stage */
- uint32_t cur_stage_group = readl(SOCFPGA_SDR_ADDRESS + addr);
-
- /* Clear the stage and substage */
- cur_stage_group &= 0xFFFF0000;
-
- /* Set the stage */
- cur_stage_group |= (set_stage & 0x000000FF);
-
- /* Write the data back */
- writel(cur_stage_group, SOCFPGA_SDR_ADDRESS + addr);
+ clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff);
}
-static void reg_file_set_sub_stage(uint32_t set_sub_stage)
+static void reg_file_set_sub_stage(u8 set_sub_stage)
{
- u32 addr = (u32)&sdr_reg_file->cur_stage;
-
- /* Read the current group and stage */
- uint32_t cur_stage_group = readl(SOCFPGA_SDR_ADDRESS + addr);
-
- /* Clear the substage */
- cur_stage_group &= 0xFFFF00FF;
-
- /* Set the sub stage */
- cur_stage_group |= ((set_sub_stage << 8) & 0x0000FF00);
-
- /* Write the data back */
- writel(cur_stage_group, SOCFPGA_SDR_ADDRESS + addr);
+ set_sub_stage &= 0xff;
+ clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);
}
-static void initialize(void)
+/**
+ * phy_mgr_initialize() - Initialize PHY Manager
+ *
+ * Initialize PHY Manager.
+ */
+static void phy_mgr_initialize(void)
{
- u32 addr = sdr_get_addr(&phy_mgr_cfg->mux_sel);
+ u32 ratio;
debug("%s:%d\n", __func__, __LINE__);
- /* USER calibration has control over path to memory */
+ /* Calibration has control over path to memory */
/*
* In Hard PHY this is a 2-bit control:
* 0: AFI Mux Select
* 1: DDIO Mux Select
*/
- writel(0x3, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x3, &phy_mgr_cfg->mux_sel);
/* USER memory clock is not stable we begin initialization */
- addr = sdr_get_addr(&phy_mgr_cfg->reset_mem_stbl);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &phy_mgr_cfg->reset_mem_stbl);
/* USER calibration status all set to zero */
- addr = sdr_get_addr(&phy_mgr_cfg->cal_status);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
-
- addr = sdr_get_addr(&phy_mgr_cfg->cal_debug_info);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
-
- if ((dyn_calib_steps & CALIB_SKIP_ALL) != CALIB_SKIP_ALL) {
- param->read_correct_mask_vg = ((uint32_t)1 <<
- (RW_MGR_MEM_DQ_PER_READ_DQS /
- RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS)) - 1;
- param->write_correct_mask_vg = ((uint32_t)1 <<
- (RW_MGR_MEM_DQ_PER_READ_DQS /
- RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS)) - 1;
- param->read_correct_mask = ((uint32_t)1 <<
- RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
- param->write_correct_mask = ((uint32_t)1 <<
- RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
- param->dm_correct_mask = ((uint32_t)1 <<
- (RW_MGR_MEM_DATA_WIDTH / RW_MGR_MEM_DATA_MASK_WIDTH))
- - 1;
- }
-}
-
-static void set_rank_and_odt_mask(uint32_t rank, uint32_t odt_mode)
-{
- uint32_t odt_mask_0 = 0;
- uint32_t odt_mask_1 = 0;
- uint32_t cs_and_odt_mask;
- uint32_t addr;
+ writel(0, &phy_mgr_cfg->cal_status);
- if (odt_mode == RW_MGR_ODT_MODE_READ_WRITE) {
- if (RW_MGR_MEM_NUMBER_OF_RANKS == 1) {
- /*
- * 1 Rank
- * Read: ODT = 0
- * Write: ODT = 1
- */
+ writel(0, &phy_mgr_cfg->cal_debug_info);
+
+ /* Init params only if we do NOT skip calibration. */
+ if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL)
+ return;
+
+ ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
+ RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
+ param->read_correct_mask_vg = (1 << ratio) - 1;
+ param->write_correct_mask_vg = (1 << ratio) - 1;
+ param->read_correct_mask = (1 << RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
+ param->write_correct_mask = (1 << RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
+ ratio = RW_MGR_MEM_DATA_WIDTH /
+ RW_MGR_MEM_DATA_MASK_WIDTH;
+ param->dm_correct_mask = (1 << ratio) - 1;
+}
+
+/**
+ * set_rank_and_odt_mask() - Set Rank and ODT mask
+ * @rank: Rank mask
+ * @odt_mode: ODT mode, OFF or READ_WRITE
+ *
+ * Set Rank and ODT mask (On-Die Termination).
+ */
+static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode)
+{
+ u32 odt_mask_0 = 0;
+ u32 odt_mask_1 = 0;
+ u32 cs_and_odt_mask;
+
+ if (odt_mode == RW_MGR_ODT_MODE_OFF) {
+ odt_mask_0 = 0x0;
+ odt_mask_1 = 0x0;
+ } else { /* RW_MGR_ODT_MODE_READ_WRITE */
+ switch (RW_MGR_MEM_NUMBER_OF_RANKS) {
+ case 1: /* 1 Rank */
+ /* Read: ODT = 0 ; Write: ODT = 1 */
odt_mask_0 = 0x0;
odt_mask_1 = 0x1;
- } else if (RW_MGR_MEM_NUMBER_OF_RANKS == 2) {
- /* 2 Ranks */
+ break;
+ case 2: /* 2 Ranks */
if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 1) {
- /* - Dual-Slot , Single-Rank
- * (1 chip-select per DIMM)
- * OR
- * - RDIMM, 4 total CS (2 CS per DIMM)
- * means 2 DIMM
- * Since MEM_NUMBER_OF_RANKS is 2 they are
- * both single rank
- * with 2 CS each (special for RDIMM)
+ /*
+ * - Dual-Slot , Single-Rank (1 CS per DIMM)
+ * OR
+ * - RDIMM, 4 total CS (2 CS per DIMM, 2 DIMM)
+ *
+ * Since MEM_NUMBER_OF_RANKS is 2, they
+ * are both single rank with 2 CS each
+ * (special for RDIMM).
+ *
* Read: Turn on ODT on the opposite rank
* Write: Turn on ODT on all ranks
*/
odt_mask_1 = 0x3;
} else {
/*
- * USER - Single-Slot , Dual-rank DIMMs
- * (2 chip-selects per DIMM)
- * USER Read: Turn on ODT off on all ranks
- * USER Write: Turn on ODT on active rank
+ * - Single-Slot , Dual-Rank (2 CS per DIMM)
+ *
+ * Read: Turn on ODT off on all ranks
+ * Write: Turn on ODT on active rank
*/
odt_mask_0 = 0x0;
odt_mask_1 = 0x3 & (1 << rank);
}
- } else {
- /* 4 Ranks
- * Read:
+ break;
+ case 4: /* 4 Ranks */
+ /* Read:
* ----------+-----------------------+
- * | |
* | ODT |
* Read From +-----------------------+
* Rank | 3 | 2 | 1 | 0 |
*
* Write:
* ----------+-----------------------+
- * | |
* | ODT |
* Write To +-----------------------+
* Rank | 3 | 2 | 1 | 0 |
odt_mask_1 = 0xA;
break;
}
+ break;
}
- } else {
- odt_mask_0 = 0x0;
- odt_mask_1 = 0x0;
}
- cs_and_odt_mask =
- (0xFF & ~(1 << rank)) |
- ((0xFF & odt_mask_0) << 8) |
- ((0xFF & odt_mask_1) << 16);
- addr = sdr_get_addr((u32 *)RW_MGR_SET_CS_AND_ODT_MASK);
- writel(cs_and_odt_mask, SOCFPGA_SDR_ADDRESS + addr);
+ cs_and_odt_mask = (0xFF & ~(1 << rank)) |
+ ((0xFF & odt_mask_0) << 8) |
+ ((0xFF & odt_mask_1) << 16);
+ writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
}
-static void scc_mgr_initialize(void)
+/**
+ * scc_mgr_set() - Set SCC Manager register
+ * @off: Base offset in SCC Manager space
+ * @grp: Read/Write group
+ * @val: Value to be set
+ *
+ * This function sets the SCC Manager (Scan Chain Control Manager) register.
+ */
+static void scc_mgr_set(u32 off, u32 grp, u32 val)
{
- u32 addr = sdr_get_addr((u32 *)SCC_MGR_HHP_RFILE);
+ writel(val, SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp << 2));
+}
+/**
+ * scc_mgr_initialize() - Initialize SCC Manager registers
+ *
+ * Initialize SCC Manager registers.
+ */
+static void scc_mgr_initialize(void)
+{
/*
- * Clear register file for HPS
- * 16 (2^4) is the size of the full register file in the scc mgr:
- * RFILE_DEPTH = log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
- * MEM_IF_READ_DQS_WIDTH - 1) + 1;
+ * Clear register file for HPS. 16 (2^4) is the size of the
+ * full register file in the scc mgr:
+ * RFILE_DEPTH = 1 + log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
+ * MEM_IF_READ_DQS_WIDTH - 1);
*/
- uint32_t i;
+ int i;
+
for (i = 0; i < 16; i++) {
debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
__func__, __LINE__, i);
- writel(0, SOCFPGA_SDR_ADDRESS + addr + (i << 2));
+ scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i);
}
}
-static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group,
- uint32_t delay)
+static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t phase)
{
- u32 addr = sdr_get_addr((u32 *)SCC_MGR_DQS_IN_DELAY);
+ scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase);
+}
- /* Load the setting in the SCC manager */
- writel(delay, SOCFPGA_SDR_ADDRESS + addr + (read_group << 2));
+static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group, uint32_t delay)
+{
+ scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay);
}
-static void scc_mgr_set_dqs_io_in_delay(uint32_t write_group,
- uint32_t delay)
+static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
{
- u32 addr = sdr_get_addr((u32 *)SCC_MGR_IO_IN_DELAY);
+ scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase);
+}
- writel(delay, SOCFPGA_SDR_ADDRESS + addr + (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
+static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
+{
+ scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
}
-static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
+static void scc_mgr_set_dqs_io_in_delay(uint32_t delay)
{
- u32 addr = sdr_get_addr((u32 *)SCC_MGR_DQS_EN_PHASE);
+ scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
+ delay);
+}
- /* Load the setting in the SCC manager */
- writel(phase, SOCFPGA_SDR_ADDRESS + addr + (read_group << 2));
+static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group, uint32_t delay)
+{
+ scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
}
-static void scc_mgr_set_dqs_en_phase_all_ranks(uint32_t read_group,
- uint32_t phase)
+static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)
{
- uint32_t r;
- uint32_t update_scan_chains;
- uint32_t addr;
+ scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay);
+}
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
- r += NUM_RANKS_PER_SHADOW_REG) {
- /*
- * USER although the h/w doesn't support different phases per
- * shadow register, for simplicity our scc manager modeling
- * keeps different phase settings per shadow reg, and it's
- * important for us to keep them in sync to match h/w.
- * for efficiency, the scan chain update should occur only
- * once to sr0.
- */
- update_scan_chains = (r == 0) ? 1 : 0;
+static void scc_mgr_set_dqs_out1_delay(uint32_t delay)
+{
+ scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
+ delay);
+}
- scc_mgr_set_dqs_en_phase(read_group, phase);
+static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
+{
+ scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
+ RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm,
+ delay);
+}
- if (update_scan_chains) {
- addr = (u32)&sdr_scc_mgr->dqs_ena;
- writel(read_group, SOCFPGA_SDR_ADDRESS + addr);
+/* load up dqs config settings */
+static void scc_mgr_load_dqs(uint32_t dqs)
+{
+ writel(dqs, &sdr_scc_mgr->dqs_ena);
+}
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
- }
- }
+/* load up dqs io config settings */
+static void scc_mgr_load_dqs_io(void)
+{
+ writel(0, &sdr_scc_mgr->dqs_io_ena);
}
-static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group,
- uint32_t phase)
+/* load up dq config settings */
+static void scc_mgr_load_dq(uint32_t dq_in_group)
{
- u32 addr = sdr_get_addr((u32 *)SCC_MGR_DQDQS_OUT_PHASE);
+ writel(dq_in_group, &sdr_scc_mgr->dq_ena);
+}
- /* Load the setting in the SCC manager */
- writel(phase, SOCFPGA_SDR_ADDRESS + addr + (write_group << 2));
+/* load up dm config settings */
+static void scc_mgr_load_dm(uint32_t dm)
+{
+ writel(dm, &sdr_scc_mgr->dm_ena);
}
-static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
- uint32_t phase)
+/**
+ * scc_mgr_set_all_ranks() - Set SCC Manager register for all ranks
+ * @off: Base offset in SCC Manager space
+ * @grp: Read/Write group
+ * @val: Value to be set
+ * @update: If non-zero, trigger SCC Manager update for all ranks
+ *
+ * This function sets the SCC Manager (Scan Chain Control Manager) register
+ * and optionally triggers the SCC update for all ranks.
+ */
+static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 val,
+ const int update)
{
- uint32_t r;
- uint32_t update_scan_chains;
- uint32_t addr;
+ u32 r;
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
r += NUM_RANKS_PER_SHADOW_REG) {
- /*
- * USER although the h/w doesn't support different phases per
- * shadow register, for simplicity our scc manager modeling
- * keeps different phase settings per shadow reg, and it's
- * important for us to keep them in sync to match h/w.
- * for efficiency, the scan chain update should occur only
- * once to sr0.
- */
- update_scan_chains = (r == 0) ? 1 : 0;
-
- scc_mgr_set_dqdqs_output_phase(write_group, phase);
+ scc_mgr_set(off, grp, val);
- if (update_scan_chains) {
- addr = (u32)&sdr_scc_mgr->dqs_ena;
- writel(write_group, SOCFPGA_SDR_ADDRESS + addr);
-
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ if (update || (r == 0)) {
+ writel(grp, &sdr_scc_mgr->dqs_ena);
+ writel(0, &sdr_scc_mgr->update);
}
}
}
-static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
+static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase)
{
- uint32_t addr = sdr_get_addr((u32 *)SCC_MGR_DQS_EN_DELAY);
+ /*
+ * USER although the h/w doesn't support different phases per
+ * shadow register, for simplicity our scc manager modeling
+ * keeps different phase settings per shadow reg, and it's
+ * important for us to keep them in sync to match h/w.
+ * for efficiency, the scan chain update should occur only
+ * once to sr0.
+ */
+ scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET,
+ read_group, phase, 0);
+}
- /* Load the setting in the SCC manager */
- writel(delay + IO_DQS_EN_DELAY_OFFSET, SOCFPGA_SDR_ADDRESS + addr +
- (read_group << 2));
+static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
+ uint32_t phase)
+{
+ /*
+ * USER although the h/w doesn't support different phases per
+ * shadow register, for simplicity our scc manager modeling
+ * keeps different phase settings per shadow reg, and it's
+ * important for us to keep them in sync to match h/w.
+ * for efficiency, the scan chain update should occur only
+ * once to sr0.
+ */
+ scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET,
+ write_group, phase, 0);
}
static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
uint32_t delay)
{
- uint32_t r;
- uint32_t addr;
-
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
- r += NUM_RANKS_PER_SHADOW_REG) {
- scc_mgr_set_dqs_en_delay(read_group, delay);
-
- addr = (u32)&sdr_scc_mgr->dqs_ena;
- writel(read_group, SOCFPGA_SDR_ADDRESS + addr);
- /*
- * In shadow register mode, the T11 settings are stored in
- * registers in the core, which are updated by the DQS_ENA
- * signals. Not issuing the SCC_MGR_UPD command allows us to
- * save lots of rank switching overhead, by calling
- * select_shadow_regs_for_update with update_scan_chains
- * set to 0.
- */
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
- }
/*
* In shadow register mode, the T11 settings are stored in
* registers in the core, which are updated by the DQS_ENA
* select_shadow_regs_for_update with update_scan_chains
* set to 0.
*/
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET,
+ read_group, delay, 1);
+ writel(0, &sdr_scc_mgr->update);
}
-static void scc_mgr_set_oct_out1_delay(uint32_t write_group, uint32_t delay)
+/**
+ * scc_mgr_set_oct_out1_delay() - Set OCT output delay
+ * @write_group: Write group
+ * @delay: Delay value
+ *
+ * This function sets the OCT output delay in SCC manager.
+ */
+static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay)
{
- uint32_t read_group;
- uint32_t addr = sdr_get_addr((u32 *)SCC_MGR_OCT_OUT1_DELAY);
-
+ const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
+ RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
+ const int base = write_group * ratio;
+ int i;
/*
* Load the setting in the SCC manager
* Although OCT affects only write data, the OCT delay is controlled
* For protocols where a write group consists of multiple read groups,
* the setting must be set multiple times.
*/
- for (read_group = write_group * RW_MGR_MEM_IF_READ_DQS_WIDTH /
- RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
- read_group < (write_group + 1) * RW_MGR_MEM_IF_READ_DQS_WIDTH /
- RW_MGR_MEM_IF_WRITE_DQS_WIDTH; ++read_group)
- writel(delay, SOCFPGA_SDR_ADDRESS + addr + (read_group << 2));
-}
-
-static void scc_mgr_set_dq_out1_delay(uint32_t write_group,
- uint32_t dq_in_group, uint32_t delay)
-{
- uint32_t addr = sdr_get_addr((u32 *)SCC_MGR_IO_OUT1_DELAY);
-
- /* Load the setting in the SCC manager */
- writel(delay, SOCFPGA_SDR_ADDRESS + addr + (dq_in_group << 2));
-}
-
-static void scc_mgr_set_dq_in_delay(uint32_t write_group,
- uint32_t dq_in_group, uint32_t delay)
-{
- uint32_t addr = sdr_get_addr((u32 *)SCC_MGR_IO_IN_DELAY);
-
- /* Load the setting in the SCC manager */
- writel(delay, SOCFPGA_SDR_ADDRESS + addr + (dq_in_group << 2));
+ for (i = 0; i < ratio; i++)
+ scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET, base + i, delay);
}
+/**
+ * scc_mgr_set_hhp_extras() - Set HHP extras.
+ *
+ * Load the fixed setting in the SCC manager HHP extras.
+ */
static void scc_mgr_set_hhp_extras(void)
{
/*
* Load the fixed setting in the SCC manager
- * bits: 0:0 = 1'b1 - dqs bypass
- * bits: 1:1 = 1'b1 - dq bypass
- * bits: 4:2 = 3'b001 - rfifo_mode
- * bits: 6:5 = 2'b01 - rfifo clock_select
- * bits: 7:7 = 1'b0 - separate gating from ungating setting
- * bits: 8:8 = 1'b0 - separate OE from Output delay setting
+ * bits: 0:0 = 1'b1 - DQS bypass
+ * bits: 1:1 = 1'b1 - DQ bypass
+ * bits: 4:2 = 3'b001 - rfifo_mode
+ * bits: 6:5 = 2'b01 - rfifo clock_select
+ * bits: 7:7 = 1'b0 - separate gating from ungating setting
+ * bits: 8:8 = 1'b0 - separate OE from Output delay setting
*/
- uint32_t value = (0<<8) | (0<<7) | (1<<5) | (1<<2) | (1<<1) | (1<<0);
- uint32_t addr = sdr_get_addr((u32 *)SCC_MGR_HHP_GLOBALS);
-
- writel(value, SOCFPGA_SDR_ADDRESS + addr + SCC_MGR_HHP_EXTRAS_OFFSET);
-}
-
-static void scc_mgr_set_dqs_out1_delay(uint32_t write_group,
- uint32_t delay)
-{
- uint32_t addr = sdr_get_addr((u32 *)SCC_MGR_IO_OUT1_DELAY);
+ const u32 value = (0 << 8) | (0 << 7) | (1 << 5) |
+ (1 << 2) | (1 << 1) | (1 << 0);
+ const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS |
+ SCC_MGR_HHP_GLOBALS_OFFSET |
+ SCC_MGR_HHP_EXTRAS_OFFSET;
- /* Load the setting in the SCC manager */
- writel(delay, SOCFPGA_SDR_ADDRESS + addr + (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
-}
-
-static void scc_mgr_set_dm_out1_delay(uint32_t write_group,
- uint32_t dm, uint32_t delay)
-{
- uint32_t addr = sdr_get_addr((u32 *)SCC_MGR_IO_OUT1_DELAY);
-
- /* Load the setting in the SCC manager */
- writel(delay, SOCFPGA_SDR_ADDRESS + addr +
- ((RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm) << 2));
+ debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n",
+ __func__, __LINE__);
+ writel(value, addr);
+ debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
+ __func__, __LINE__);
}
-/*
- * USER Zero all DQS config
- * TODO: maybe rename to scc_mgr_zero_dqs_config (or something)
+/**
+ * scc_mgr_zero_all() - Zero all DQS config
+ *
+ * Zero all DQS config.
*/
static void scc_mgr_zero_all(void)
{
- uint32_t i, r;
- uint32_t addr;
+ int i, r;
/*
* USER Zero all DQS config settings, across all groups and all
* shadow registers
*/
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r +=
- NUM_RANKS_PER_SHADOW_REG) {
+ for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
+ r += NUM_RANKS_PER_SHADOW_REG) {
for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
/*
* The phases actually don't exist on a per-rank basis,
for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
scc_mgr_set_dqdqs_output_phase(i, 0);
- /* av/cv don't have out2 */
+ /* Arria V/Cyclone V don't have out2. */
scc_mgr_set_oct_out1_delay(i, IO_DQS_OUT_RESERVE);
}
}
- /* multicast to all DQS group enables */
- addr = (u32)&sdr_scc_mgr->dqs_ena;
- writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
-
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ /* Multicast to all DQS group enables. */
+ writel(0xff, &sdr_scc_mgr->dqs_ena);
+ writel(0, &sdr_scc_mgr->update);
}
-static void scc_set_bypass_mode(uint32_t write_group, uint32_t mode)
+/**
+ * scc_set_bypass_mode() - Set bypass mode and trigger SCC update
+ * @write_group: Write group
+ *
+ * Set bypass mode and trigger SCC update.
+ */
+static void scc_set_bypass_mode(const u32 write_group)
{
- uint32_t addr;
- /* mode = 0 : Do NOT bypass - Half Rate Mode */
- /* mode = 1 : Bypass - Full Rate Mode */
-
- /* only need to set once for all groups, pins, dq, dqs, dm */
- if (write_group == 0) {
- debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n", __func__,
- __LINE__);
- scc_mgr_set_hhp_extras();
- debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
- __func__, __LINE__);
- }
- /* multicast to all DQ enables */
- addr = (u32)&sdr_scc_mgr->dq_ena;
- writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
+ /* Multicast to all DQ enables. */
+ writel(0xff, &sdr_scc_mgr->dq_ena);
+ writel(0xff, &sdr_scc_mgr->dm_ena);
- addr = (u32)&sdr_scc_mgr->dm_ena;
- writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
+ /* Update current DQS IO enable. */
+ writel(0, &sdr_scc_mgr->dqs_io_ena);
- /* update current DQS IO enable */
- addr = (u32)&sdr_scc_mgr->dqs_io_ena;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ /* Update the DQS logic. */
+ writel(write_group, &sdr_scc_mgr->dqs_ena);
- /* update the DQS logic */
- addr = (u32)&sdr_scc_mgr->dqs_ena;
- writel(write_group, SOCFPGA_SDR_ADDRESS + addr);
+ /* Hit update. */
+ writel(0, &sdr_scc_mgr->update);
+}
- /* hit update */
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+/**
+ * scc_mgr_load_dqs_for_write_group() - Load DQS settings for Write Group
+ * @write_group: Write group
+ *
+ * Load DQS settings for Write Group, do not trigger SCC update.
+ */
+static void scc_mgr_load_dqs_for_write_group(const u32 write_group)
+{
+ const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
+ RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
+ const int base = write_group * ratio;
+ int i;
+ /*
+ * Load the setting in the SCC manager
+ * Although OCT affects only write data, the OCT delay is controlled
+ * by the DQS logic block which is instantiated once per read group.
+ * For protocols where a write group consists of multiple read groups,
+ * the setting must be set multiple times.
+ */
+ for (i = 0; i < ratio; i++)
+ writel(base + i, &sdr_scc_mgr->dqs_ena);
}
-static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin,
- int32_t out_only)
+/**
+ * scc_mgr_zero_group() - Zero all configs for a group
+ *
+ * Zero DQ, DM, DQS and OCT configs for a group.
+ */
+static void scc_mgr_zero_group(const u32 write_group, const int out_only)
{
- uint32_t i, r;
- uint32_t addr;
+ int i, r;
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r +=
- NUM_RANKS_PER_SHADOW_REG) {
- /* Zero all DQ config settings */
+ for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
+ r += NUM_RANKS_PER_SHADOW_REG) {
+ /* Zero all DQ config settings. */
for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
- scc_mgr_set_dq_out1_delay(write_group, i, 0);
+ scc_mgr_set_dq_out1_delay(i, 0);
if (!out_only)
- scc_mgr_set_dq_in_delay(write_group, i, 0);
+ scc_mgr_set_dq_in_delay(i, 0);
}
- /* multicast to all DQ enables */
- addr = (u32)&sdr_scc_mgr->dq_ena;
- writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
+ /* Multicast to all DQ enables. */
+ writel(0xff, &sdr_scc_mgr->dq_ena);
- /* Zero all DM config settings */
- for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
- scc_mgr_set_dm_out1_delay(write_group, i, 0);
- }
+ /* Zero all DM config settings. */
+ for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
+ scc_mgr_set_dm_out1_delay(i, 0);
- /* multicast to all DM enables */
- addr = (u32)&sdr_scc_mgr->dm_ena;
- writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
+ /* Multicast to all DM enables. */
+ writel(0xff, &sdr_scc_mgr->dm_ena);
- /* zero all DQS io settings */
+ /* Zero all DQS IO settings. */
if (!out_only)
- scc_mgr_set_dqs_io_in_delay(write_group, 0);
- /* av/cv don't have out2 */
- scc_mgr_set_dqs_out1_delay(write_group, IO_DQS_OUT_RESERVE);
+ scc_mgr_set_dqs_io_in_delay(0);
+
+ /* Arria V/Cyclone V don't have out2. */
+ scc_mgr_set_dqs_out1_delay(IO_DQS_OUT_RESERVE);
scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
scc_mgr_load_dqs_for_write_group(write_group);
- /* multicast to all DQS IO enables (only 1) */
- addr = (u32)&sdr_scc_mgr->dqs_io_ena;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ /* Multicast to all DQS IO enables (only 1 in total). */
+ writel(0, &sdr_scc_mgr->dqs_io_ena);
- /* hit update to zero everything */
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ /* Hit update to zero everything. */
+ writel(0, &sdr_scc_mgr->update);
}
}
-/* load up dqs config settings */
-static void scc_mgr_load_dqs(uint32_t dqs)
-{
- uint32_t addr = (u32)&sdr_scc_mgr->dqs_ena;
-
- writel(dqs, SOCFPGA_SDR_ADDRESS + addr);
-}
-
-static void scc_mgr_load_dqs_for_write_group(uint32_t write_group)
-{
- uint32_t read_group;
- uint32_t addr = (u32)&sdr_scc_mgr->dqs_ena;
- /*
- * Although OCT affects only write data, the OCT delay is controlled
- * by the DQS logic block which is instantiated once per read group.
- * For protocols where a write group consists of multiple read groups,
- * the setting must be scanned multiple times.
- */
- for (read_group = write_group * RW_MGR_MEM_IF_READ_DQS_WIDTH /
- RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
- read_group < (write_group + 1) * RW_MGR_MEM_IF_READ_DQS_WIDTH /
- RW_MGR_MEM_IF_WRITE_DQS_WIDTH; ++read_group)
- writel(read_group, SOCFPGA_SDR_ADDRESS + addr);
-}
-
-/* load up dqs io config settings */
-static void scc_mgr_load_dqs_io(void)
-{
- uint32_t addr = (u32)&sdr_scc_mgr->dqs_io_ena;
-
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
-}
-
-/* load up dq config settings */
-static void scc_mgr_load_dq(uint32_t dq_in_group)
-{
- uint32_t addr = (u32)&sdr_scc_mgr->dq_ena;
-
- writel(dq_in_group, SOCFPGA_SDR_ADDRESS + addr);
-}
-
-/* load up dm config settings */
-static void scc_mgr_load_dm(uint32_t dm)
-{
- uint32_t addr = (u32)&sdr_scc_mgr->dm_ena;
-
- writel(dm, SOCFPGA_SDR_ADDRESS + addr);
-}
-
/*
* apply and load a particular input delay for the DQ pins in a group
* group_bgn is the index of the first dq pin (in the write group)
*/
-static void scc_mgr_apply_group_dq_in_delay(uint32_t write_group,
- uint32_t group_bgn, uint32_t delay)
+static void scc_mgr_apply_group_dq_in_delay(uint32_t group_bgn, uint32_t delay)
{
uint32_t i, p;
for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
- scc_mgr_set_dq_in_delay(write_group, p, delay);
+ scc_mgr_set_dq_in_delay(p, delay);
scc_mgr_load_dq(p);
}
}
-/* apply and load a particular output delay for the DQ pins in a group */
-static void scc_mgr_apply_group_dq_out1_delay(uint32_t write_group,
- uint32_t group_bgn,
- uint32_t delay1)
+/**
+ * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group
+ * @delay: Delay value
+ *
+ * Apply and load a particular output delay for the DQ pins in a group.
+ */
+static void scc_mgr_apply_group_dq_out1_delay(const u32 delay)
{
- uint32_t i, p;
+ int i;
- for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
- scc_mgr_set_dq_out1_delay(write_group, i, delay1);
+ for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
+ scc_mgr_set_dq_out1_delay(i, delay);
scc_mgr_load_dq(i);
}
}
/* apply and load a particular output delay for the DM pins in a group */
-static void scc_mgr_apply_group_dm_out1_delay(uint32_t write_group,
- uint32_t delay1)
+static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1)
{
uint32_t i;
for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
- scc_mgr_set_dm_out1_delay(write_group, i, delay1);
+ scc_mgr_set_dm_out1_delay(i, delay1);
scc_mgr_load_dm(i);
}
}
static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,
uint32_t delay)
{
- scc_mgr_set_dqs_out1_delay(write_group, delay);
+ scc_mgr_set_dqs_out1_delay(delay);
scc_mgr_load_dqs_io();
scc_mgr_set_oct_out1_delay(write_group, delay);
scc_mgr_load_dqs_for_write_group(write_group);
}
-/* apply a delay to the entire output side: DQ, DM, DQS, OCT */
-static void scc_mgr_apply_group_all_out_delay_add(uint32_t write_group,
- uint32_t group_bgn,
- uint32_t delay)
+/**
+ * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side: DQ, DM, DQS, OCT
+ * @write_group: Write group
+ * @delay: Delay value
+ *
+ * Apply a delay to the entire output side: DQ, DM, DQS, OCT.
+ */
+static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,
+ const u32 delay)
{
- uint32_t i, p, new_delay;
-
- /* dq shift */
- for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
- new_delay = READ_SCC_DQ_OUT2_DELAY;
- new_delay += delay;
-
- if (new_delay > IO_IO_OUT2_DELAY_MAX) {
- debug_cond(DLEVEL == 1, "%s:%d (%u, %u, %u) DQ[%u,%u]:\
- %u > %lu => %lu", __func__, __LINE__,
- write_group, group_bgn, delay, i, p, new_delay,
- (long unsigned int)IO_IO_OUT2_DELAY_MAX,
- (long unsigned int)IO_IO_OUT2_DELAY_MAX);
- new_delay = IO_IO_OUT2_DELAY_MAX;
- }
+ u32 i, new_delay;
+ /* DQ shift */
+ for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++)
scc_mgr_load_dq(i);
- }
-
- /* dm shift */
- for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
- new_delay = READ_SCC_DM_IO_OUT2_DELAY;
- new_delay += delay;
-
- if (new_delay > IO_IO_OUT2_DELAY_MAX) {
- debug_cond(DLEVEL == 1, "%s:%d (%u, %u, %u) DM[%u]:\
- %u > %lu => %lu\n", __func__, __LINE__,
- write_group, group_bgn, delay, i, new_delay,
- (long unsigned int)IO_IO_OUT2_DELAY_MAX,
- (long unsigned int)IO_IO_OUT2_DELAY_MAX);
- new_delay = IO_IO_OUT2_DELAY_MAX;
- }
+ /* DM shift */
+ for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
scc_mgr_load_dm(i);
- }
-
- /* dqs shift */
- new_delay = READ_SCC_DQS_IO_OUT2_DELAY;
- new_delay += delay;
+ /* DQS shift */
+ new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay;
if (new_delay > IO_IO_OUT2_DELAY_MAX) {
- debug_cond(DLEVEL == 1, "%s:%d (%u, %u, %u) DQS: %u > %d => %d;"
- " adding %u to OUT1\n", __func__, __LINE__,
- write_group, group_bgn, delay, new_delay,
- IO_IO_OUT2_DELAY_MAX, IO_IO_OUT2_DELAY_MAX,
+ debug_cond(DLEVEL == 1,
+ "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
+ __func__, __LINE__, write_group, delay, new_delay,
+ IO_IO_OUT2_DELAY_MAX,
new_delay - IO_IO_OUT2_DELAY_MAX);
- scc_mgr_set_dqs_out1_delay(write_group, new_delay -
- IO_IO_OUT2_DELAY_MAX);
- new_delay = IO_IO_OUT2_DELAY_MAX;
+ new_delay -= IO_IO_OUT2_DELAY_MAX;
+ scc_mgr_set_dqs_out1_delay(new_delay);
}
scc_mgr_load_dqs_io();
- /* oct shift */
- new_delay = READ_SCC_OCT_OUT2_DELAY;
- new_delay += delay;
-
+ /* OCT shift */
+ new_delay = READ_SCC_OCT_OUT2_DELAY + delay;
if (new_delay > IO_IO_OUT2_DELAY_MAX) {
- debug_cond(DLEVEL == 1, "%s:%d (%u, %u, %u) DQS: %u > %d => %d;"
- " adding %u to OUT1\n", __func__, __LINE__,
- write_group, group_bgn, delay, new_delay,
- IO_IO_OUT2_DELAY_MAX, IO_IO_OUT2_DELAY_MAX,
+ debug_cond(DLEVEL == 1,
+ "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
+ __func__, __LINE__, write_group, delay,
+ new_delay, IO_IO_OUT2_DELAY_MAX,
new_delay - IO_IO_OUT2_DELAY_MAX);
- scc_mgr_set_oct_out1_delay(write_group, new_delay -
- IO_IO_OUT2_DELAY_MAX);
- new_delay = IO_IO_OUT2_DELAY_MAX;
+ new_delay -= IO_IO_OUT2_DELAY_MAX;
+ scc_mgr_set_oct_out1_delay(write_group, new_delay);
}
scc_mgr_load_dqs_for_write_group(write_group);
}
-/*
- * USER apply a delay to the entire output side (DQ, DM, DQS, OCT)
- * and to all ranks
+/**
+ * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side to all ranks
+ * @write_group: Write group
+ * @delay: Delay value
+ *
+ * Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks.
*/
-static void scc_mgr_apply_group_all_out_delay_add_all_ranks(
- uint32_t write_group, uint32_t group_bgn, uint32_t delay)
+static void
+scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group,
+ const u32 delay)
{
- uint32_t r;
- uint32_t addr = (u32)&sdr_scc_mgr->update;
+ int r;
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
- r += NUM_RANKS_PER_SHADOW_REG) {
- scc_mgr_apply_group_all_out_delay_add(write_group,
- group_bgn, delay);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ r += NUM_RANKS_PER_SHADOW_REG) {
+ scc_mgr_apply_group_all_out_delay_add(write_group, delay);
+ writel(0, &sdr_scc_mgr->update);
}
}
-/* optimization used to recover some slots in ddr3 inst_rom */
-/* could be applied to other protocols if we wanted to */
+/**
+ * set_jump_as_return() - Return instruction optimization
+ *
+ * Optimization used to recover some slots in ddr3 inst_rom could be
+ * applied to other protocols if we wanted to
+ */
static void set_jump_as_return(void)
{
- uint32_t addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr0);
-
/*
- * to save space, we replace return with jump to special shared
+ * To save space, we replace return with jump to special shared
* RETURN instruction so we set the counter to large value so that
- * we always jump
+ * we always jump.
*/
- writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add0);
- writel(RW_MGR_RETURN, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
+ writel(RW_MGR_RETURN, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
}
/*
uint8_t inner = 0;
uint8_t outer = 0;
uint16_t c_loop = 0;
- uint32_t addr;
debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
* overhead
*/
if (afi_clocks <= 0x100) {
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr1);
- writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner), SOCFPGA_SDR_ADDRESS + addr);
+ writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
+ &sdr_rw_load_mgr_regs->load_cntr1);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add1);
- writel(RW_MGR_IDLE_LOOP1, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_IDLE_LOOP1,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
- writel(RW_MGR_IDLE_LOOP1, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_IDLE_LOOP1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET);
} else {
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr0);
- writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner), SOCFPGA_SDR_ADDRESS + addr);
+ writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
+ &sdr_rw_load_mgr_regs->load_cntr0);
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr1);
- writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer), SOCFPGA_SDR_ADDRESS + addr);
+ writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
+ &sdr_rw_load_mgr_regs->load_cntr1);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add0);
- writel(RW_MGR_IDLE_LOOP2, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_IDLE_LOOP2,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add0);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add1);
- writel(RW_MGR_IDLE_LOOP2, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_IDLE_LOOP2,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
/* hack to get around compiler not being smart enough */
if (afi_clocks <= 0x10000) {
/* only need to run once */
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
- writel(RW_MGR_IDLE_LOOP2, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_IDLE_LOOP2, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET);
} else {
do {
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
- writel(RW_MGR_IDLE_LOOP2, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_IDLE_LOOP2,
+ SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET);
} while (c_loop-- != 0);
}
}
debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
}
-static void rw_mgr_mem_initialize(void)
+/**
+ * rw_mgr_mem_init_load_regs() - Load instruction registers
+ * @cntr0: Counter 0 value
+ * @cntr1: Counter 1 value
+ * @cntr2: Counter 2 value
+ * @jump: Jump instruction value
+ *
+ * Load instruction registers.
+ */
+static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)
{
- uint32_t r;
- uint32_t addr;
-
- debug("%s:%d\n", __func__, __LINE__);
-
- /* The reset / cke part of initialization is broadcasted to all ranks */
- addr = sdr_get_addr((u32 *)RW_MGR_SET_CS_AND_ODT_MASK);
- writel(RW_MGR_RANK_ALL, SOCFPGA_SDR_ADDRESS + addr);
-
- /*
- * Here's how you load register for a loop
- * Counters are located @ 0x800
- * Jump address are located @ 0xC00
- * For both, registers 0 to 3 are selected using bits 3 and 2, like
- * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
- * I know this ain't pretty, but Avalon bus throws away the 2 least
- * significant bits
- */
-
- /* start with memory RESET activated */
-
- /* tINIT = 200us */
-
- /*
- * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
- * If a and b are the number of iteration in 2 nested loops
- * it takes the following number of cycles to complete the operation:
- * number_of_cycles = ((2 + n) * a + 2) * b
- * where n is the number of instruction in the inner loop
- * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
- * b = 6A
- */
+ uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET;
/* Load counters */
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr0);
- writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR0_VAL),
- SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr1);
- writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR1_VAL),
- SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr2);
- writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR2_VAL),
- SOCFPGA_SDR_ADDRESS + addr);
+ writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr0),
+ &sdr_rw_load_mgr_regs->load_cntr0);
+ writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr1),
+ &sdr_rw_load_mgr_regs->load_cntr1);
+ writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr2),
+ &sdr_rw_load_mgr_regs->load_cntr2);
/* Load jump address */
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add0);
- writel(RW_MGR_INIT_RESET_0_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
-
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add1);
- writel(RW_MGR_INIT_RESET_0_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
-
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add2);
- writel(RW_MGR_INIT_RESET_0_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
+ writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
/* Execute count instruction */
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
- writel(RW_MGR_INIT_RESET_0_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
-
- /* indicate that memory is stable */
- addr = sdr_get_addr(&phy_mgr_cfg->reset_mem_stbl);
- writel(1, SOCFPGA_SDR_ADDRESS + addr);
-
- /*
- * transition the RESET to high
- * Wait for 500us
- */
-
- /*
- * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
- * If a and b are the number of iteration in 2 nested loops
- * it takes the following number of cycles to complete the operation
- * number_of_cycles = ((2 + n) * a + 2) * b
- * where n is the number of instruction in the inner loop
- * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
- * b = FF
- */
-
- /* Load counters */
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr0);
- writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR0_VAL),
- SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr1);
- writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR1_VAL),
- SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr2);
- writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR2_VAL),
- SOCFPGA_SDR_ADDRESS + addr);
-
- /* Load jump address */
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add0);
- writel(RW_MGR_INIT_RESET_1_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add1);
- writel(RW_MGR_INIT_RESET_1_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add2);
- writel(RW_MGR_INIT_RESET_1_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
-
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
- writel(RW_MGR_INIT_RESET_1_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
-
- /* bring up clock enable */
+ writel(jump, grpaddr);
+}
- /* tXRP < 250 ck cycles */
- delay_for_n_mem_clocks(250);
+/**
+ * rw_mgr_mem_load_user() - Load user calibration values
+ * @fin1: Final instruction 1
+ * @fin2: Final instruction 2
+ * @precharge: If 1, precharge the banks at the end
+ *
+ * Load user calibration values and optionally precharge the banks.
+ */
+static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2,
+ const int precharge)
+{
+ u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET;
+ u32 r;
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
if (param->skip_ranks[r]) {
/* set rank */
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
+ /* precharge all banks ... */
+ if (precharge)
+ writel(RW_MGR_PRECHARGE_ALL, grpaddr);
+
/*
* USER Use Mirror-ed commands for odd ranks if address
* mirrorring is on
*/
if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
set_jump_as_return();
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
- writel(RW_MGR_MRS2_MIRR, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MRS2_MIRR, grpaddr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS3_MIRR, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MRS3_MIRR, grpaddr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS1_MIRR, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MRS1_MIRR, grpaddr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS0_DLL_RESET_MIRR, SOCFPGA_SDR_ADDRESS + addr);
+ writel(fin1, grpaddr);
} else {
set_jump_as_return();
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
- writel(RW_MGR_MRS2, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MRS2, grpaddr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS3, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MRS3, grpaddr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS1, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MRS1, grpaddr);
set_jump_as_return();
- writel(RW_MGR_MRS0_DLL_RESET, SOCFPGA_SDR_ADDRESS + addr);
+ writel(fin2, grpaddr);
}
+
+ if (precharge)
+ continue;
+
set_jump_as_return();
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
- writel(RW_MGR_ZQCL, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_ZQCL, grpaddr);
/* tZQinit = tDLLK = 512 ck cycles */
delay_for_n_mem_clocks(512);
}
}
-/*
- * At the end of calibration we have to program the user settings in, and
- * USER hand off the memory to the user.
+/**
+ * rw_mgr_mem_initialize() - Initialize RW Manager
+ *
+ * Initialize RW Manager.
*/
-static void rw_mgr_mem_handoff(void)
+static void rw_mgr_mem_initialize(void)
{
- uint32_t r;
- uint32_t addr;
-
debug("%s:%d\n", __func__, __LINE__);
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
- if (param->skip_ranks[r])
- /* request to skip the rank */
- continue;
- /* set rank */
- set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
- /* precharge all banks ... */
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
- writel(RW_MGR_PRECHARGE_ALL, SOCFPGA_SDR_ADDRESS + addr);
+ /* The reset / cke part of initialization is broadcasted to all ranks */
+ writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
- /* load up MR settings specified by user */
+ /*
+ * Here's how you load register for a loop
+ * Counters are located @ 0x800
+ * Jump address are located @ 0xC00
+ * For both, registers 0 to 3 are selected using bits 3 and 2, like
+ * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
+ * I know this ain't pretty, but Avalon bus throws away the 2 least
+ * significant bits
+ */
- /*
- * Use Mirror-ed commands for odd ranks if address
- * mirrorring is on
- */
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
- if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
- set_jump_as_return();
- writel(RW_MGR_MRS2_MIRR, SOCFPGA_SDR_ADDRESS + addr);
- delay_for_n_mem_clocks(4);
- set_jump_as_return();
- writel(RW_MGR_MRS3_MIRR, SOCFPGA_SDR_ADDRESS + addr);
- delay_for_n_mem_clocks(4);
- set_jump_as_return();
- writel(RW_MGR_MRS1_MIRR, SOCFPGA_SDR_ADDRESS + addr);
- delay_for_n_mem_clocks(4);
- set_jump_as_return();
- writel(RW_MGR_MRS0_USER_MIRR, SOCFPGA_SDR_ADDRESS + addr);
- } else {
- set_jump_as_return();
- writel(RW_MGR_MRS2, SOCFPGA_SDR_ADDRESS + addr);
- delay_for_n_mem_clocks(4);
- set_jump_as_return();
- writel(RW_MGR_MRS3, SOCFPGA_SDR_ADDRESS + addr);
- delay_for_n_mem_clocks(4);
- set_jump_as_return();
- writel(RW_MGR_MRS1, SOCFPGA_SDR_ADDRESS + addr);
- delay_for_n_mem_clocks(4);
- set_jump_as_return();
- writel(RW_MGR_MRS0_USER, SOCFPGA_SDR_ADDRESS + addr);
- }
- /*
- * USER need to wait tMOD (12CK or 15ns) time before issuing
- * other commands, but we will have plenty of NIOS cycles before
- * actual handoff so its okay.
- */
- }
+ /* Start with memory RESET activated */
+
+ /* tINIT = 200us */
+
+ /*
+ * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
+ * If a and b are the number of iteration in 2 nested loops
+ * it takes the following number of cycles to complete the operation:
+ * number_of_cycles = ((2 + n) * a + 2) * b
+ * where n is the number of instruction in the inner loop
+ * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
+ * b = 6A
+ */
+ rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL, SEQ_TINIT_CNTR1_VAL,
+ SEQ_TINIT_CNTR2_VAL,
+ RW_MGR_INIT_RESET_0_CKE_0);
+
+ /* Indicate that memory is stable. */
+ writel(1, &phy_mgr_cfg->reset_mem_stbl);
+
+ /*
+ * transition the RESET to high
+ * Wait for 500us
+ */
+
+ /*
+ * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
+ * If a and b are the number of iteration in 2 nested loops
+ * it takes the following number of cycles to complete the operation
+ * number_of_cycles = ((2 + n) * a + 2) * b
+ * where n is the number of instruction in the inner loop
+ * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
+ * b = FF
+ */
+ rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL, SEQ_TRESET_CNTR1_VAL,
+ SEQ_TRESET_CNTR2_VAL,
+ RW_MGR_INIT_RESET_1_CKE_0);
+
+ /* Bring up clock enable. */
+
+ /* tXRP < 250 ck cycles */
+ delay_for_n_mem_clocks(250);
+
+ rw_mgr_mem_load_user(RW_MGR_MRS0_DLL_RESET_MIRR, RW_MGR_MRS0_DLL_RESET,
+ 0);
}
/*
- * performs a guaranteed read on the patterns we are going to use during a
- * read test to ensure memory works
+ * At the end of calibration we have to program the user settings in, and
+ * USER hand off the memory to the user.
*/
-static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn,
- uint32_t group, uint32_t num_tries, uint32_t *bit_chk,
- uint32_t all_ranks)
+static void rw_mgr_mem_handoff(void)
{
- uint32_t r, vg;
- uint32_t correct_mask_vg;
- uint32_t tmp_bit_chk;
- uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
- (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
- uint32_t addr;
- uint32_t base_rw_mgr;
+ rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR, RW_MGR_MRS0_USER, 1);
+ /*
+ * USER need to wait tMOD (12CK or 15ns) time before issuing
+ * other commands, but we will have plenty of NIOS cycles before
+ * actual handoff so its okay.
+ */
+}
- *bit_chk = param->read_correct_mask;
- correct_mask_vg = param->read_correct_mask_vg;
+/**
+ * rw_mgr_mem_calibrate_read_test_patterns() - Read back test patterns
+ * @rank_bgn: Rank number
+ * @group: Read/Write Group
+ * @all_ranks: Test all ranks
+ *
+ * Performs a guaranteed read on the patterns we are going to use during a
+ * read test to ensure memory works.
+ */
+static int
+rw_mgr_mem_calibrate_read_test_patterns(const u32 rank_bgn, const u32 group,
+ const u32 all_ranks)
+{
+ const u32 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET;
+ const u32 addr_offset =
+ (group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS) << 2;
+ const u32 rank_end = all_ranks ?
+ RW_MGR_MEM_NUMBER_OF_RANKS :
+ (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
+ const u32 shift_ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
+ RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
+ const u32 correct_mask_vg = param->read_correct_mask_vg;
+
+ u32 tmp_bit_chk, base_rw_mgr, bit_chk;
+ int vg, r;
+ int ret = 0;
+
+ bit_chk = param->read_correct_mask;
for (r = rank_bgn; r < rank_end; r++) {
+ /* Request to skip the rank */
if (param->skip_ranks[r])
- /* request to skip the rank */
continue;
- /* set rank */
+ /* Set rank */
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
/* Load up a constant bursts of read commands */
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr0);
- writel(0x20, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add0);
- writel(RW_MGR_GUARANTEED_READ, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
+ writel(RW_MGR_GUARANTEED_READ,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add0);
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr1);
- writel(0x20, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add1);
- writel(RW_MGR_GUARANTEED_READ_CONT, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
+ writel(RW_MGR_GUARANTEED_READ_CONT,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
tmp_bit_chk = 0;
- for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
- /* reset the fifos to get pointers to known state */
-
- addr = sdr_get_addr(&phy_mgr_cmd->fifo_reset);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr((u32 *)RW_MGR_RESET_READ_DATAPATH);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
-
- tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
- / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
-
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
- writel(RW_MGR_GUARANTEED_READ, SOCFPGA_SDR_ADDRESS + addr +
- ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
- vg) << 2));
-
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
- base_rw_mgr = readl(SOCFPGA_SDR_ADDRESS + addr);
- tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & (~base_rw_mgr));
-
- if (vg == 0)
- break;
+ for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1;
+ vg >= 0; vg--) {
+ /* Reset the FIFOs to get pointers to known state. */
+ writel(0, &phy_mgr_cmd->fifo_reset);
+ writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RESET_READ_DATAPATH_OFFSET);
+ writel(RW_MGR_GUARANTEED_READ,
+ addr + addr_offset + (vg << 2));
+
+ base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
+ tmp_bit_chk <<= shift_ratio;
+ tmp_bit_chk |= correct_mask_vg & ~base_rw_mgr;
}
- *bit_chk &= tmp_bit_chk;
+
+ bit_chk &= tmp_bit_chk;
}
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
- writel(RW_MGR_CLEAR_DQS_ENABLE, SOCFPGA_SDR_ADDRESS + addr + (group << 2));
+ writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
- debug_cond(DLEVEL == 1, "%s:%d test_load_patterns(%u,ALL) => (%u == %u) =>\
- %lu\n", __func__, __LINE__, group, *bit_chk, param->read_correct_mask,
- (long unsigned int)(*bit_chk == param->read_correct_mask));
- return *bit_chk == param->read_correct_mask;
-}
-static uint32_t rw_mgr_mem_calibrate_read_test_patterns_all_ranks
- (uint32_t group, uint32_t num_tries, uint32_t *bit_chk)
-{
- return rw_mgr_mem_calibrate_read_test_patterns(0, group,
- num_tries, bit_chk, 1);
+ if (bit_chk != param->read_correct_mask)
+ ret = -EIO;
+
+ debug_cond(DLEVEL == 1,
+ "%s:%d test_load_patterns(%u,ALL) => (%u == %u) => %i\n",
+ __func__, __LINE__, group, bit_chk,
+ param->read_correct_mask, ret);
+
+ return ret;
}
-/* load up the patterns we are going to use during a read test */
-static void rw_mgr_mem_calibrate_read_load_patterns(uint32_t rank_bgn,
- uint32_t all_ranks)
+/**
+ * rw_mgr_mem_calibrate_read_load_patterns() - Load up the patterns for read test
+ * @rank_bgn: Rank number
+ * @all_ranks: Test all ranks
+ *
+ * Load up the patterns we are going to use during a read test.
+ */
+static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn,
+ const int all_ranks)
{
- uint32_t r;
- uint32_t addr;
- uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
- (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
+ const u32 rank_end = all_ranks ?
+ RW_MGR_MEM_NUMBER_OF_RANKS :
+ (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
+ u32 r;
debug("%s:%d\n", __func__, __LINE__);
+
for (r = rank_bgn; r < rank_end; r++) {
if (param->skip_ranks[r])
/* request to skip the rank */
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
/* Load up a constant bursts */
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr0);
- writel(0x20, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add0);
- writel(RW_MGR_GUARANTEED_WRITE_WAIT0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_GUARANTEED_WRITE_WAIT0,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add0);
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr1);
- writel(0x20, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add1);
- writel(RW_MGR_GUARANTEED_WRITE_WAIT1, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_GUARANTEED_WRITE_WAIT1,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr2);
- writel(0x04, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add2);
- writel(RW_MGR_GUARANTEED_WRITE_WAIT2, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_GUARANTEED_WRITE_WAIT2,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr3);
- writel(0x04, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add3);
- writel(RW_MGR_GUARANTEED_WRITE_WAIT3, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_GUARANTEED_WRITE_WAIT3,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
- writel(RW_MGR_GUARANTEED_WRITE, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_GUARANTEED_WRITE, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET);
}
set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
/* set rank */
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr1);
- writel(0x10, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add1);
- writel(RW_MGR_READ_B2B_WAIT1, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_READ_B2B_WAIT1,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr2);
- writel(0x10, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add2);
- writel(RW_MGR_READ_B2B_WAIT2, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
+ writel(RW_MGR_READ_B2B_WAIT2,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr0);
if (quick_read_mode)
- writel(0x1, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
/* need at least two (1+1) reads to capture failures */
else if (all_groups)
- writel(0x06, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0);
else
- writel(0x32, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add0);
- writel(RW_MGR_READ_B2B, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr3);
+ writel(RW_MGR_READ_B2B,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add0);
if (all_groups)
writel(RW_MGR_MEM_IF_READ_DQS_WIDTH *
RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
- SOCFPGA_SDR_ADDRESS + addr);
+ &sdr_rw_load_mgr_regs->load_cntr3);
else
- writel(0x0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add3);
- writel(RW_MGR_READ_B2B, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_READ_B2B,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
tmp_bit_chk = 0;
for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
/* reset the fifos to get pointers to known state */
- addr = sdr_get_addr(&phy_mgr_cmd->fifo_reset);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr((u32 *)RW_MGR_RESET_READ_DATAPATH);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &phy_mgr_cmd->fifo_reset);
+ writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RESET_READ_DATAPATH_OFFSET);
tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
/ RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
- addr = sdr_get_addr((u32 *)(all_groups ? RW_MGR_RUN_ALL_GROUPS :
- RW_MGR_RUN_SINGLE_GROUP));
- writel(RW_MGR_READ_B2B, SOCFPGA_SDR_ADDRESS + addr +
+ if (all_groups)
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_ALL_GROUPS_OFFSET;
+ else
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
+
+ writel(RW_MGR_READ_B2B, addr +
((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
vg) << 2));
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
- base_rw_mgr = readl(SOCFPGA_SDR_ADDRESS + addr);
+ base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
if (vg == 0)
*bit_chk &= tmp_bit_chk;
}
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
- writel(RW_MGR_CLEAR_DQS_ENABLE, SOCFPGA_SDR_ADDRESS + addr + (group << 2));
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
+ writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
if (all_correct) {
set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
bit_chk, all_groups, 1);
}
-static void rw_mgr_incr_vfifo(uint32_t grp, uint32_t *v)
+/**
+ * rw_mgr_incr_vfifo() - Increase VFIFO value
+ * @grp: Read/Write group
+ *
+ * Increase VFIFO value.
+ */
+static void rw_mgr_incr_vfifo(const u32 grp)
{
- uint32_t addr = sdr_get_addr(&phy_mgr_cmd->inc_vfifo_hard_phy);
-
- writel(grp, SOCFPGA_SDR_ADDRESS + addr);
- (*v)++;
+ writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
}
-static void rw_mgr_decr_vfifo(uint32_t grp, uint32_t *v)
+/**
+ * rw_mgr_decr_vfifo() - Decrease VFIFO value
+ * @grp: Read/Write group
+ *
+ * Decrease VFIFO value.
+ */
+static void rw_mgr_decr_vfifo(const u32 grp)
{
- uint32_t i;
+ u32 i;
- for (i = 0; i < VFIFO_SIZE-1; i++)
- rw_mgr_incr_vfifo(grp, v);
+ for (i = 0; i < VFIFO_SIZE - 1; i++)
+ rw_mgr_incr_vfifo(grp);
}
-static int find_vfifo_read(uint32_t grp, uint32_t *bit_chk)
+/**
+ * find_vfifo_failing_read() - Push VFIFO to get a failing read
+ * @grp: Read/Write group
+ *
+ * Push VFIFO until a failing read happens.
+ */
+static int find_vfifo_failing_read(const u32 grp)
{
- uint32_t v;
- uint32_t fail_cnt = 0;
- uint32_t test_status;
+ u32 v, ret, bit_chk, fail_cnt = 0;
- for (v = 0; v < VFIFO_SIZE; ) {
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo %u\n",
+ for (v = 0; v < VFIFO_SIZE; v++) {
+ debug_cond(DLEVEL == 2, "%s:%d: vfifo %u\n",
__func__, __LINE__, v);
- test_status = rw_mgr_mem_calibrate_read_test_all_ranks
- (grp, 1, PASS_ONE_BIT, bit_chk, 0);
- if (!test_status) {
+ ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
+ PASS_ONE_BIT, &bit_chk, 0);
+ if (!ret) {
fail_cnt++;
if (fail_cnt == 2)
- break;
+ return v;
}
- /* fiddle with FIFO */
- rw_mgr_incr_vfifo(grp, &v);
+ /* Fiddle with FIFO. */
+ rw_mgr_incr_vfifo(grp);
}
- if (v >= VFIFO_SIZE) {
- /* no failing read found!! Something must have gone wrong */
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo failed\n",
- __func__, __LINE__);
- return 0;
- } else {
- return v;
- }
+ /* No failing read found! Something must have gone wrong. */
+ debug_cond(DLEVEL == 2, "%s:%d: vfifo failed\n", __func__, __LINE__);
+ return 0;
}
-static int find_working_phase(uint32_t *grp, uint32_t *bit_chk,
- uint32_t dtaps_per_ptap, uint32_t *work_bgn,
- uint32_t *v, uint32_t *d, uint32_t *p,
- uint32_t *i, uint32_t *max_working_cnt)
+/**
+ * sdr_find_phase() - Find DQS enable phase
+ * @working: If 1, look for working phase, if 0, look for non-working phase
+ * @grp: Read/Write group
+ * @work: Working window position
+ * @i: Iterator
+ * @p: DQS Phase Iterator
+ *
+ * Find working or non-working DQS enable phase setting.
+ */
+static int sdr_find_phase(int working, const u32 grp, u32 *work,
+ u32 *i, u32 *p)
{
- uint32_t found_begin = 0;
- uint32_t tmp_delay = 0;
- uint32_t test_status;
+ u32 ret, bit_chk;
+ const u32 end = VFIFO_SIZE + (working ? 0 : 1);
- for (*d = 0; *d <= dtaps_per_ptap; (*d)++, tmp_delay +=
- IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
- *work_bgn = tmp_delay;
- scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
-
- for (*i = 0; *i < VFIFO_SIZE; (*i)++) {
- for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_bgn +=
- IO_DELAY_PER_OPA_TAP) {
- scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
+ for (; *i < end; (*i)++) {
+ if (working)
+ *p = 0;
- test_status =
- rw_mgr_mem_calibrate_read_test_all_ranks
- (*grp, 1, PASS_ONE_BIT, bit_chk, 0);
+ for (; *p <= IO_DQS_EN_PHASE_MAX; (*p)++) {
+ scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
- if (test_status) {
- *max_working_cnt = 1;
- found_begin = 1;
- break;
- }
- }
+ ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
+ PASS_ONE_BIT, &bit_chk, 0);
+ if (!working)
+ ret = !ret;
- if (found_begin)
- break;
+ if (ret)
+ return 0;
- if (*p > IO_DQS_EN_PHASE_MAX)
- /* fiddle with FIFO */
- rw_mgr_incr_vfifo(*grp, v);
+ *work += IO_DELAY_PER_OPA_TAP;
}
- if (found_begin)
- break;
+ if (*p > IO_DQS_EN_PHASE_MAX) {
+ /* Fiddle with FIFO. */
+ rw_mgr_incr_vfifo(grp);
+ if (!working)
+ *p = 0;
+ }
}
- if (*i >= VFIFO_SIZE) {
- /* cannot find working solution */
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/\
- ptap/dtap\n", __func__, __LINE__);
- return 0;
- } else {
- return 1;
+ return -EINVAL;
+}
+
+/**
+ * sdr_working_phase() - Find working DQS enable phase
+ * @grp: Read/Write group
+ * @work_bgn: Working window start position
+ * @d: dtaps output value
+ * @p: DQS Phase Iterator
+ * @i: Iterator
+ *
+ * Find working DQS enable phase setting.
+ */
+static int sdr_working_phase(const u32 grp, u32 *work_bgn, u32 *d,
+ u32 *p, u32 *i)
+{
+ const u32 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP /
+ IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
+ int ret;
+
+ *work_bgn = 0;
+
+ for (*d = 0; *d <= dtaps_per_ptap; (*d)++) {
+ *i = 0;
+ scc_mgr_set_dqs_en_delay_all_ranks(grp, *d);
+ ret = sdr_find_phase(1, grp, work_bgn, i, p);
+ if (!ret)
+ return 0;
+ *work_bgn += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
}
+
+ /* Cannot find working solution */
+ debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/ptap/dtap\n",
+ __func__, __LINE__);
+ return -EINVAL;
}
-static void sdr_backup_phase(uint32_t *grp, uint32_t *bit_chk,
- uint32_t *work_bgn, uint32_t *v, uint32_t *d,
- uint32_t *p, uint32_t *max_working_cnt)
+/**
+ * sdr_backup_phase() - Find DQS enable backup phase
+ * @grp: Read/Write group
+ * @work_bgn: Working window start position
+ * @p: DQS Phase Iterator
+ *
+ * Find DQS enable backup phase setting.
+ */
+static void sdr_backup_phase(const u32 grp, u32 *work_bgn, u32 *p)
{
- uint32_t found_begin = 0;
- uint32_t tmp_delay;
+ u32 tmp_delay, bit_chk, d;
+ int ret;
/* Special case code for backing up a phase */
if (*p == 0) {
*p = IO_DQS_EN_PHASE_MAX;
- rw_mgr_decr_vfifo(*grp, v);
+ rw_mgr_decr_vfifo(grp);
} else {
(*p)--;
}
tmp_delay = *work_bgn - IO_DELAY_PER_OPA_TAP;
- scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
+ scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
- for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn;
- (*d)++, tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
- scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
+ for (d = 0; d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn; d++) {
+ scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
- if (rw_mgr_mem_calibrate_read_test_all_ranks(*grp, 1,
- PASS_ONE_BIT,
- bit_chk, 0)) {
- found_begin = 1;
+ ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
+ PASS_ONE_BIT, &bit_chk, 0);
+ if (ret) {
*work_bgn = tmp_delay;
break;
}
- }
- /* We have found a working dtap before the ptap found above */
- if (found_begin == 1)
- (*max_working_cnt)++;
+ tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
+ }
- /*
- * Restore VFIFO to old state before we decremented it
- * (if needed).
- */
+ /* Restore VFIFO to old state before we decremented it (if needed). */
(*p)++;
if (*p > IO_DQS_EN_PHASE_MAX) {
*p = 0;
- rw_mgr_incr_vfifo(*grp, v);
+ rw_mgr_incr_vfifo(grp);
}
- scc_mgr_set_dqs_en_delay_all_ranks(*grp, 0);
+ scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
}
-static int sdr_nonworking_phase(uint32_t *grp, uint32_t *bit_chk,
- uint32_t *work_bgn, uint32_t *v, uint32_t *d,
- uint32_t *p, uint32_t *i, uint32_t *max_working_cnt,
- uint32_t *work_end)
+/**
+ * sdr_nonworking_phase() - Find non-working DQS enable phase
+ * @grp: Read/Write group
+ * @work_end: Working window end position
+ * @p: DQS Phase Iterator
+ * @i: Iterator
+ *
+ * Find non-working DQS enable phase setting.
+ */
+static int sdr_nonworking_phase(const u32 grp, u32 *work_end, u32 *p, u32 *i)
{
- uint32_t found_end = 0;
+ int ret;
(*p)++;
*work_end += IO_DELAY_PER_OPA_TAP;
if (*p > IO_DQS_EN_PHASE_MAX) {
- /* fiddle with FIFO */
+ /* Fiddle with FIFO. */
*p = 0;
- rw_mgr_incr_vfifo(*grp, v);
+ rw_mgr_incr_vfifo(grp);
}
- for (; *i < VFIFO_SIZE + 1; (*i)++) {
- for (; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_end
- += IO_DELAY_PER_OPA_TAP) {
- scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
-
- if (!rw_mgr_mem_calibrate_read_test_all_ranks
- (*grp, 1, PASS_ONE_BIT, bit_chk, 0)) {
- found_end = 1;
- break;
- } else {
- (*max_working_cnt)++;
- }
- }
-
- if (found_end)
- break;
-
- if (*p > IO_DQS_EN_PHASE_MAX) {
- /* fiddle with FIFO */
- rw_mgr_incr_vfifo(*grp, v);
- *p = 0;
- }
+ ret = sdr_find_phase(0, grp, work_end, i, p);
+ if (ret) {
+ /* Cannot see edge of failing read. */
+ debug_cond(DLEVEL == 2, "%s:%d: end: failed\n",
+ __func__, __LINE__);
}
- if (*i >= VFIFO_SIZE + 1) {
- /* cannot see edge of failing read */
- debug_cond(DLEVEL == 2, "%s:%d sdr_nonworking_phase: end:\
- failed\n", __func__, __LINE__);
- return 0;
- } else {
- return 1;
- }
+ return ret;
}
-static int sdr_find_window_centre(uint32_t *grp, uint32_t *bit_chk,
- uint32_t *work_bgn, uint32_t *v, uint32_t *d,
- uint32_t *p, uint32_t *work_mid,
- uint32_t *work_end)
+/**
+ * sdr_find_window_center() - Find center of the working DQS window.
+ * @grp: Read/Write group
+ * @work_bgn: First working settings
+ * @work_end: Last working settings
+ *
+ * Find center of the working DQS enable window.
+ */
+static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
+ const u32 work_end)
{
- int i;
+ u32 bit_chk, work_mid;
int tmp_delay = 0;
+ int i, p, d;
- *work_mid = (*work_bgn + *work_end) / 2;
+ work_mid = (work_bgn + work_end) / 2;
debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
- *work_bgn, *work_end, *work_mid);
+ work_bgn, work_end, work_mid);
/* Get the middle delay to be less than a VFIFO delay */
- for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX;
- (*p)++, tmp_delay += IO_DELAY_PER_OPA_TAP)
- ;
+ tmp_delay = (IO_DQS_EN_PHASE_MAX + 1) * IO_DELAY_PER_OPA_TAP;
+
debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
- while (*work_mid > tmp_delay)
- *work_mid -= tmp_delay;
- debug_cond(DLEVEL == 2, "new work_mid %d\n", *work_mid);
+ work_mid %= tmp_delay;
+ debug_cond(DLEVEL == 2, "new work_mid %d\n", work_mid);
- tmp_delay = 0;
- for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX && tmp_delay < *work_mid;
- (*p)++, tmp_delay += IO_DELAY_PER_OPA_TAP)
- ;
- tmp_delay -= IO_DELAY_PER_OPA_TAP;
- debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", (*p) - 1, tmp_delay);
- for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_mid; (*d)++,
- tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP)
- ;
- debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", *d, tmp_delay);
+ tmp_delay = rounddown(work_mid, IO_DELAY_PER_OPA_TAP);
+ if (tmp_delay > IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP)
+ tmp_delay = IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP;
+ p = tmp_delay / IO_DELAY_PER_OPA_TAP;
+
+ debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", p, tmp_delay);
- scc_mgr_set_dqs_en_phase_all_ranks(*grp, (*p) - 1);
- scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
+ d = DIV_ROUND_UP(work_mid - tmp_delay, IO_DELAY_PER_DQS_EN_DCHAIN_TAP);
+ if (d > IO_DQS_EN_DELAY_MAX)
+ d = IO_DQS_EN_DELAY_MAX;
+ tmp_delay += d * IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
+
+ debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", d, tmp_delay);
+
+ scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
+ scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
/*
* push vfifo until we can successfully calibrate. We can do this
* because the largest possible margin in 1 VFIFO cycle.
*/
for (i = 0; i < VFIFO_SIZE; i++) {
- debug_cond(DLEVEL == 2, "find_dqs_en_phase: center: vfifo=%u\n",
- *v);
- if (rw_mgr_mem_calibrate_read_test_all_ranks(*grp, 1,
+ debug_cond(DLEVEL == 2, "find_dqs_en_phase: center\n");
+ if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
PASS_ONE_BIT,
- bit_chk, 0)) {
- break;
+ &bit_chk, 0)) {
+ debug_cond(DLEVEL == 2,
+ "%s:%d center: found: ptap=%u dtap=%u\n",
+ __func__, __LINE__, p, d);
+ return 0;
}
- /* fiddle with FIFO */
- rw_mgr_incr_vfifo(*grp, v);
+ /* Fiddle with FIFO. */
+ rw_mgr_incr_vfifo(grp);
}
- if (i >= VFIFO_SIZE) {
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: center: \
- failed\n", __func__, __LINE__);
- return 0;
- } else {
- return 1;
- }
+ debug_cond(DLEVEL == 2, "%s:%d center: failed.\n",
+ __func__, __LINE__);
+ return -EINVAL;
}
/* find a good dqs enable to use */
-static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
+static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(u32 grp)
{
- uint32_t v, d, p, i;
- uint32_t max_working_cnt;
+ uint32_t d, p, i;
uint32_t bit_chk;
uint32_t dtaps_per_ptap;
- uint32_t work_bgn, work_mid, work_end;
+ uint32_t work_bgn, work_end;
uint32_t found_passing_read, found_failing_read, initial_failing_dtap;
- uint32_t addr;
debug("%s:%d %u\n", __func__, __LINE__, grp);
scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
- /* ************************************************************** */
- /* * Step 0 : Determine number of delay taps for each phase tap * */
- dtaps_per_ptap = IO_DELAY_PER_OPA_TAP/IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
-
- /* ********************************************************* */
- /* * Step 1 : First push vfifo until we get a failing read * */
- v = find_vfifo_read(grp, &bit_chk);
+ /* Step 0: Determine number of delay taps for each phase tap. */
+ dtaps_per_ptap = IO_DELAY_PER_OPA_TAP / IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
- max_working_cnt = 0;
+ /* Step 1: First push vfifo until we get a failing read. */
+ find_vfifo_failing_read(grp);
- /* ******************************************************** */
- /* * step 2: find first working phase, increment in ptaps * */
+ /* Step 2: Find first working phase, increment in ptaps. */
work_bgn = 0;
- if (find_working_phase(&grp, &bit_chk, dtaps_per_ptap, &work_bgn, &v, &d,
- &p, &i, &max_working_cnt) == 0)
+ if (sdr_working_phase(grp, &work_bgn, &d, &p, &i))
return 0;
work_end = work_bgn;
/*
- * If d is 0 then the working window covers a phase tap and
- * we can follow the old procedure otherwise, we've found the beginning,
+ * If d is 0 then the working window covers a phase tap and we can
+ * follow the old procedure. Otherwise, we've found the beginning
* and we need to increment the dtaps until we find the end.
*/
if (d == 0) {
- /* ********************************************************* */
- /* * step 3a: if we have room, back off by one and
- increment in dtaps * */
-
- sdr_backup_phase(&grp, &bit_chk, &work_bgn, &v, &d, &p,
- &max_working_cnt);
-
- /* ********************************************************* */
- /* * step 4a: go forward from working phase to non working
- phase, increment in ptaps * */
- if (sdr_nonworking_phase(&grp, &bit_chk, &work_bgn, &v, &d, &p,
- &i, &max_working_cnt, &work_end) == 0)
+ /*
+ * Step 3a: If we have room, back off by one and
+ * increment in dtaps.
+ */
+ sdr_backup_phase(grp, &work_bgn, &p);
+
+ /*
+ * Step 4a: go forward from working phase to non working
+ * phase, increment in ptaps.
+ */
+ if (sdr_nonworking_phase(grp, &work_end, &p, &i))
return 0;
- /* ********************************************************* */
- /* * step 5a: back off one from last, increment in dtaps * */
+ /* Step 5a: Back off one from last, increment in dtaps. */
/* Special case code for backing up a phase */
if (p == 0) {
p = IO_DQS_EN_PHASE_MAX;
- rw_mgr_decr_vfifo(grp, &v);
+ rw_mgr_decr_vfifo(grp);
} else {
p = p - 1;
}
work_end -= IO_DELAY_PER_OPA_TAP;
scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
- /* * The actual increment of dtaps is done outside of
- the if/else loop to share code */
d = 0;
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p: \
- vfifo=%u ptap=%u\n", __func__, __LINE__,
- v, p);
- } else {
- /* ******************************************************* */
- /* * step 3-5b: Find the right edge of the window using
- delay taps * */
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase:vfifo=%u \
- ptap=%u dtap=%u bgn=%u\n", __func__, __LINE__,
- v, p, d, work_bgn);
-
- work_end = work_bgn;
+ debug_cond(DLEVEL == 2, "%s:%d p: ptap=%u\n",
+ __func__, __LINE__, p);
+ }
- /* * The actual increment of dtaps is done outside of the
- if/else loop to share code */
+ /* The dtap increment to find the failing edge is done here. */
+ for (; d <= IO_DQS_EN_DELAY_MAX; d++) {
+ debug_cond(DLEVEL == 2, "%s:%d end-2: dtap=%u\n",
+ __func__, __LINE__, d);
- /* Only here to counterbalance a subtract later on which is
- not needed if this branch of the algorithm is taken */
- max_working_cnt++;
- }
+ scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
- /* The dtap increment to find the failing edge is done here */
- for (; d <= IO_DQS_EN_DELAY_MAX; d++, work_end +=
- IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
- end-2: dtap=%u\n", __func__, __LINE__, d);
- scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
+ if (!rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
+ PASS_ONE_BIT,
+ &bit_chk, 0)) {
+ break;
+ }
- if (!rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
- PASS_ONE_BIT,
- &bit_chk, 0)) {
- break;
- }
+ work_end += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
}
/* Go back to working dtap */
if (d != 0)
work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p/d: vfifo=%u \
- ptap=%u dtap=%u end=%u\n", __func__, __LINE__,
- v, p, d-1, work_end);
+ debug_cond(DLEVEL == 2,
+ "%s:%d p/d: ptap=%u dtap=%u end=%u\n",
+ __func__, __LINE__, p, d - 1, work_end);
if (work_end < work_bgn) {
/* nil range */
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: end-2: \
- failed\n", __func__, __LINE__);
+ debug_cond(DLEVEL == 2, "%s:%d end-2: failed\n",
+ __func__, __LINE__);
return 0;
}
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: found range [%u,%u]\n",
+ debug_cond(DLEVEL == 2, "%s:%d found range [%u,%u]\n",
__func__, __LINE__, work_bgn, work_end);
- /* *************************************************************** */
/*
- * * We need to calculate the number of dtaps that equal a ptap
- * * To do that we'll back up a ptap and re-find the edge of the
- * * window using dtaps
+ * We need to calculate the number of dtaps that equal a ptap.
+ * To do that we'll back up a ptap and re-find the edge of the
+ * window using dtaps
*/
-
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: calculate dtaps_per_ptap \
- for tracking\n", __func__, __LINE__);
+ debug_cond(DLEVEL == 2, "%s:%d calculate dtaps_per_ptap for tracking\n",
+ __func__, __LINE__);
/* Special case code for backing up a phase */
if (p == 0) {
p = IO_DQS_EN_PHASE_MAX;
- rw_mgr_decr_vfifo(grp, &v);
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
- cycle/phase: v=%u p=%u\n", __func__, __LINE__,
- v, p);
+ rw_mgr_decr_vfifo(grp);
+ debug_cond(DLEVEL == 2, "%s:%d backedup cycle/phase: p=%u\n",
+ __func__, __LINE__, p);
} else {
p = p - 1;
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
- phase only: v=%u p=%u", __func__, __LINE__,
- v, p);
+ debug_cond(DLEVEL == 2, "%s:%d backedup phase only: p=%u",
+ __func__, __LINE__, p);
}
scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
/*
* Increase dtap until we first see a passing read (in case the
- * window is smaller than a ptap),
- * and then a failing read to mark the edge of the window again
+ * window is smaller than a ptap), and then a failing read to
+ * mark the edge of the window again.
*/
- /* Find a passing read */
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find passing read\n",
+ /* Find a passing read. */
+ debug_cond(DLEVEL == 2, "%s:%d find passing read\n",
__func__, __LINE__);
found_passing_read = 0;
found_failing_read = 0;
initial_failing_dtap = d;
for (; d <= IO_DQS_EN_DELAY_MAX; d++) {
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: testing \
- read d=%u\n", __func__, __LINE__, d);
+ debug_cond(DLEVEL == 2, "%s:%d testing read d=%u\n",
+ __func__, __LINE__, d);
scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
}
if (found_passing_read) {
- /* Find a failing read */
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find failing \
- read\n", __func__, __LINE__);
+ /* Find a failing read. */
+ debug_cond(DLEVEL == 2, "%s:%d find failing read\n",
+ __func__, __LINE__);
for (d = d + 1; d <= IO_DQS_EN_DELAY_MAX; d++) {
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
- testing read d=%u\n", __func__, __LINE__, d);
+ debug_cond(DLEVEL == 2, "%s:%d testing read d=%u\n",
+ __func__, __LINE__, d);
scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
if (!rw_mgr_mem_calibrate_read_test_all_ranks
}
}
} else {
- debug_cond(DLEVEL == 1, "%s:%d find_dqs_en_phase: failed to \
- calculate dtaps", __func__, __LINE__);
- debug_cond(DLEVEL == 1, "per ptap. Fall back on static value\n");
+ debug_cond(DLEVEL == 1,
+ "%s:%d failed to calculate dtaps per ptap. Fall back on static value\n",
+ __func__, __LINE__);
}
/*
if (found_passing_read && found_failing_read)
dtaps_per_ptap = d - initial_failing_dtap;
- addr = (u32)&sdr_reg_file->dtaps_per_ptap;
- writel(dtaps_per_ptap, SOCFPGA_SDR_ADDRESS + addr);
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: dtaps_per_ptap=%u \
- - %u = %u", __func__, __LINE__, d,
- initial_failing_dtap, dtaps_per_ptap);
+ writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
+ debug_cond(DLEVEL == 2, "%s:%d dtaps_per_ptap=%u - %u = %u",
+ __func__, __LINE__, d, initial_failing_dtap, dtaps_per_ptap);
- /* ******************************************** */
- /* * step 6: Find the centre of the window * */
- if (sdr_find_window_centre(&grp, &bit_chk, &work_bgn, &v, &d, &p,
- &work_mid, &work_end) == 0)
+ /* Step 6: Find the centre of the window. */
+ if (sdr_find_window_centre(grp, work_bgn, work_end))
return 0;
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: center found: \
- vfifo=%u ptap=%u dtap=%u\n", __func__, __LINE__,
- v, p-1, d);
return 1;
}
-/*
- * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
- * dq_in_delay values
- */
-static uint32_t
-rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
-(uint32_t write_group, uint32_t read_group, uint32_t test_bgn)
-{
- uint32_t found;
- uint32_t i;
- uint32_t p;
- uint32_t d;
- uint32_t r;
- uint32_t addr;
-
- const uint32_t delay_step = IO_IO_IN_DELAY_MAX /
- (RW_MGR_MEM_DQ_PER_READ_DQS-1);
- /* we start at zero, so have one less dq to devide among */
-
- debug("%s:%d (%u,%u,%u)", __func__, __LINE__, write_group, read_group,
- test_bgn);
-
- /* try different dq_in_delays since the dq path is shorter than dqs */
-
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
- r += NUM_RANKS_PER_SHADOW_REG) {
- for (i = 0, p = test_bgn, d = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS;
- i++, p++, d += delay_step) {
- debug_cond(DLEVEL == 1, "%s:%d rw_mgr_mem_calibrate_\
- vfifo_find_dqs_", __func__, __LINE__);
- debug_cond(DLEVEL == 1, "en_phase_sweep_dq_in_delay: g=%u/%u ",
- write_group, read_group);
- debug_cond(DLEVEL == 1, "r=%u, i=%u p=%u d=%u\n", r, i , p, d);
- scc_mgr_set_dq_in_delay(write_group, p, d);
- scc_mgr_load_dq(p);
- }
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
- }
-
- found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(read_group);
-
- debug_cond(DLEVEL == 1, "%s:%d rw_mgr_mem_calibrate_vfifo_find_dqs_\
- en_phase_sweep_dq", __func__, __LINE__);
- debug_cond(DLEVEL == 1, "_in_delay: g=%u/%u found=%u; Reseting delay \
- chain to zero\n", write_group, read_group, found);
-
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
- r += NUM_RANKS_PER_SHADOW_REG) {
- for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS;
- i++, p++) {
- scc_mgr_set_dq_in_delay(write_group, p, 0);
- scc_mgr_load_dq(p);
- }
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
- }
-
- return found;
-}
-
/* per-bit deskew DQ and center */
static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
debug("%s:%d: %u %u", __func__, __LINE__, read_group, test_bgn);
- addr = sdr_get_addr((u32 *)SCC_MGR_DQS_IN_DELAY);
- start_dqs = readl(SOCFPGA_SDR_ADDRESS + addr + (read_group << 2));
+ addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
+ start_dqs = readl(addr + (read_group << 2));
if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
- start_dqs_en = readl(SOCFPGA_SDR_ADDRESS + addr + ((read_group << 2)
+ start_dqs_en = readl(addr + ((read_group << 2)
- IO_DQS_EN_DELAY_OFFSET));
/* set the left and right edge of each bit to an illegal value */
right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
}
- addr = (u32)&sdr_scc_mgr->update;
/* Search for the left edge of the window for each bit */
for (d = 0; d <= IO_IO_IN_DELAY_MAX; d++) {
scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, d);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &sdr_scc_mgr->update);
/*
* Stop searching when the read test doesn't pass AND when
}
/* Reset DQ delay chains to 0 */
- scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, 0);
+ scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
sticky_bit_chk = 0;
for (i = RW_MGR_MEM_DQ_PER_READ_DQS - 1;; i--) {
debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
break;
}
- addr = (u32)&sdr_scc_mgr->update;
/* Search for the right edge of the window for each bit */
for (d = 0; d <= IO_DQS_IN_DELAY_MAX - start_dqs; d++) {
scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
}
scc_mgr_load_dqs(read_group);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &sdr_scc_mgr->update);
/*
* Stop searching when the read test doesn't pass AND when
}
/* Check that all bits have a window */
- addr = (u32)&sdr_scc_mgr->update;
for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
%d right_edge[%u]: %d", __func__, __LINE__,
start_dqs_en);
}
scc_mgr_load_dqs(read_group);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &sdr_scc_mgr->update);
debug_cond(DLEVEL == 1, "%s:%d vfifo_center: failed to \
find edge [%u]: %d %d", __func__, __LINE__,
dqs_margin = IO_IO_IN_DELAY_MAX + 1;
dq_margin = IO_IO_IN_DELAY_MAX + 1;
- addr = sdr_get_addr((u32 *)SCC_MGR_IO_IN_DELAY);
/* add delay to bring centre of all DQ windows to the same "level" */
for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
/* Use values before divide by 2 to reduce round off error */
debug_cond(DLEVEL == 2, "vfifo_center: before: \
shift_dq[%u]=%d\n", i, shift_dq);
- temp_dq_in_delay1 = readl(SOCFPGA_SDR_ADDRESS + addr + (p << 2));
- temp_dq_in_delay2 = readl(SOCFPGA_SDR_ADDRESS + addr + (i << 2));
+ addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
+ temp_dq_in_delay1 = readl(addr + (p << 2));
+ temp_dq_in_delay2 = readl(addr + (i << 2));
+
+ if (shift_dq + (int32_t)temp_dq_in_delay1 >
+ (int32_t)IO_IO_IN_DELAY_MAX) {
+ shift_dq = (int32_t)IO_IO_IN_DELAY_MAX - temp_dq_in_delay2;
+ } else if (shift_dq + (int32_t)temp_dq_in_delay1 < 0) {
+ shift_dq = -(int32_t)temp_dq_in_delay1;
+ }
+ debug_cond(DLEVEL == 2, "vfifo_center: after: \
+ shift_dq[%u]=%d\n", i, shift_dq);
+ final_dq[i] = temp_dq_in_delay1 + shift_dq;
+ scc_mgr_set_dq_in_delay(p, final_dq[i]);
+ scc_mgr_load_dq(p);
+
+ debug_cond(DLEVEL == 2, "vfifo_center: margin[%u]=[%d,%d]\n", i,
+ left_edge[i] - shift_dq + (-mid_min),
+ right_edge[i] + shift_dq - (-mid_min));
+ /* To determine values for export structures */
+ if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
+ dq_margin = left_edge[i] - shift_dq + (-mid_min);
+
+ if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
+ dqs_margin = right_edge[i] + shift_dq - (-mid_min);
+ }
+
+ final_dqs = new_dqs;
+ if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
+ final_dqs_en = start_dqs_en - mid_min;
+
+ /* Move DQS-en */
+ if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
+ scc_mgr_set_dqs_en_delay(read_group, final_dqs_en);
+ scc_mgr_load_dqs(read_group);
+ }
+
+ /* Move DQS */
+ scc_mgr_set_dqs_bus_in_delay(read_group, final_dqs);
+ scc_mgr_load_dqs(read_group);
+ debug_cond(DLEVEL == 2, "%s:%d vfifo_center: dq_margin=%d \
+ dqs_margin=%d", __func__, __LINE__,
+ dq_margin, dqs_margin);
+
+ /*
+ * Do not remove this line as it makes sure all of our decisions
+ * have been applied. Apply the update bit.
+ */
+ writel(0, &sdr_scc_mgr->update);
+
+ return (dq_margin >= 0) && (dqs_margin >= 0);
+}
+
+/**
+ * rw_mgr_mem_calibrate_guaranteed_write() - Perform guaranteed write into the device
+ * @rw_group: Read/Write Group
+ * @phase: DQ/DQS phase
+ *
+ * Because initially no communication ca be reliably performed with the memory
+ * device, the sequencer uses a guaranteed write mechanism to write data into
+ * the memory device.
+ */
+static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group,
+ const u32 phase)
+{
+ int ret;
+
+ /* Set a particular DQ/DQS phase. */
+ scc_mgr_set_dqdqs_output_phase_all_ranks(rw_group, phase);
+
+ debug_cond(DLEVEL == 1, "%s:%d guaranteed write: g=%u p=%u\n",
+ __func__, __LINE__, rw_group, phase);
+
+ /*
+ * Altera EMI_RM 2015.05.04 :: Figure 1-25
+ * Load up the patterns used by read calibration using the
+ * current DQDQS phase.
+ */
+ rw_mgr_mem_calibrate_read_load_patterns(0, 1);
+
+ if (gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ)
+ return 0;
+
+ /*
+ * Altera EMI_RM 2015.05.04 :: Figure 1-26
+ * Back-to-Back reads of the patterns used for calibration.
+ */
+ ret = rw_mgr_mem_calibrate_read_test_patterns(0, rw_group, 1);
+ if (ret)
+ debug_cond(DLEVEL == 1,
+ "%s:%d Guaranteed read test failed: g=%u p=%u\n",
+ __func__, __LINE__, rw_group, phase);
+ return ret;
+}
+
+/**
+ * rw_mgr_mem_calibrate_dqs_enable_calibration() - DQS Enable Calibration
+ * @rw_group: Read/Write Group
+ * @test_bgn: Rank at which the test begins
+ *
+ * DQS enable calibration ensures reliable capture of the DQ signal without
+ * glitches on the DQS line.
+ */
+static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
+ const u32 test_bgn)
+{
+ /*
+ * Altera EMI_RM 2015.05.04 :: Figure 1-27
+ * DQS and DQS Eanble Signal Relationships.
+ */
+
+ /* We start at zero, so have one less dq to devide among */
+ const u32 delay_step = IO_IO_IN_DELAY_MAX /
+ (RW_MGR_MEM_DQ_PER_READ_DQS - 1);
+ int found;
+ u32 i, p, d, r;
+
+ debug("%s:%d (%u,%u)\n", __func__, __LINE__, rw_group, test_bgn);
+
+ /* Try different dq_in_delays since the DQ path is shorter than DQS. */
+ for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
+ r += NUM_RANKS_PER_SHADOW_REG) {
+ for (i = 0, p = test_bgn, d = 0;
+ i < RW_MGR_MEM_DQ_PER_READ_DQS;
+ i++, p++, d += delay_step) {
+ debug_cond(DLEVEL == 1,
+ "%s:%d: g=%u r=%u i=%u p=%u d=%u\n",
+ __func__, __LINE__, rw_group, r, i, p, d);
+
+ scc_mgr_set_dq_in_delay(p, d);
+ scc_mgr_load_dq(p);
+ }
+
+ writel(0, &sdr_scc_mgr->update);
+ }
- if (shift_dq + (int32_t)temp_dq_in_delay1 >
- (int32_t)IO_IO_IN_DELAY_MAX) {
- shift_dq = (int32_t)IO_IO_IN_DELAY_MAX - temp_dq_in_delay2;
- } else if (shift_dq + (int32_t)temp_dq_in_delay1 < 0) {
- shift_dq = -(int32_t)temp_dq_in_delay1;
- }
- debug_cond(DLEVEL == 2, "vfifo_center: after: \
- shift_dq[%u]=%d\n", i, shift_dq);
- final_dq[i] = temp_dq_in_delay1 + shift_dq;
- scc_mgr_set_dq_in_delay(write_group, p, final_dq[i]);
- scc_mgr_load_dq(p);
+ /*
+ * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
+ * dq_in_delay values
+ */
+ found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(rw_group);
- debug_cond(DLEVEL == 2, "vfifo_center: margin[%u]=[%d,%d]\n", i,
- left_edge[i] - shift_dq + (-mid_min),
- right_edge[i] + shift_dq - (-mid_min));
- /* To determine values for export structures */
- if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
- dq_margin = left_edge[i] - shift_dq + (-mid_min);
+ debug_cond(DLEVEL == 1,
+ "%s:%d: g=%u found=%u; Reseting delay chain to zero\n",
+ __func__, __LINE__, rw_group, found);
- if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
- dqs_margin = right_edge[i] + shift_dq - (-mid_min);
+ for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
+ r += NUM_RANKS_PER_SHADOW_REG) {
+ scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
+ writel(0, &sdr_scc_mgr->update);
}
- final_dqs = new_dqs;
- if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
- final_dqs_en = start_dqs_en - mid_min;
+ if (!found)
+ return -EINVAL;
- /* Move DQS-en */
- if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
- scc_mgr_set_dqs_en_delay(read_group, final_dqs_en);
- scc_mgr_load_dqs(read_group);
- }
+ return 0;
- /* Move DQS */
- scc_mgr_set_dqs_bus_in_delay(read_group, final_dqs);
- scc_mgr_load_dqs(read_group);
- debug_cond(DLEVEL == 2, "%s:%d vfifo_center: dq_margin=%d \
- dqs_margin=%d", __func__, __LINE__,
- dq_margin, dqs_margin);
+}
+
+/**
+ * rw_mgr_mem_calibrate_dq_dqs_centering() - Centering DQ/DQS
+ * @rw_group: Read/Write Group
+ * @test_bgn: Rank at which the test begins
+ * @use_read_test: Perform a read test
+ * @update_fom: Update FOM
+ *
+ * The centerin DQ/DQS stage attempts to align DQ and DQS signals on reads
+ * within a group.
+ */
+static int
+rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group, const u32 test_bgn,
+ const int use_read_test,
+ const int update_fom)
+
+{
+ int ret, grp_calibrated;
+ u32 rank_bgn, sr;
/*
- * Do not remove this line as it makes sure all of our decisions
- * have been applied. Apply the update bit.
+ * Altera EMI_RM 2015.05.04 :: Figure 1-28
+ * Read per-bit deskew can be done on a per shadow register basis.
*/
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ grp_calibrated = 1;
+ for (rank_bgn = 0, sr = 0;
+ rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
+ rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
+ /* Check if this set of ranks should be skipped entirely. */
+ if (param->skip_shadow_regs[sr])
+ continue;
- return (dq_margin >= 0) && (dqs_margin >= 0);
+ ret = rw_mgr_mem_calibrate_vfifo_center(rank_bgn, rw_group,
+ rw_group, test_bgn,
+ use_read_test,
+ update_fom);
+ if (ret)
+ continue;
+
+ grp_calibrated = 0;
+ }
+
+ if (!grp_calibrated)
+ return -EIO;
+
+ return 0;
}
-/*
- * calibrate the read valid prediction FIFO.
+/**
+ * rw_mgr_mem_calibrate_vfifo() - Calibrate the read valid prediction FIFO
+ * @rw_group: Read/Write Group
+ * @test_bgn: Rank at which the test begins
+ *
+ * Stage 1: Calibrate the read valid prediction FIFO.
*
- * - read valid prediction will consist of finding a good DQS enable phase,
- * DQS enable delay, DQS input phase, and DQS input delay.
+ * This function implements UniPHY calibration Stage 1, as explained in
+ * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
+ *
+ * - read valid prediction will consist of finding:
+ * - DQS enable phase and DQS enable delay (DQS Enable Calibration)
+ * - DQS input phase and DQS input delay (DQ/DQS Centering)
* - we also do a per-bit deskew on the DQ lines.
*/
-static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,
- uint32_t test_bgn)
+static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)
{
- uint32_t p, d, rank_bgn, sr;
+ uint32_t p, d;
uint32_t dtaps_per_ptap;
- uint32_t tmp_delay;
- uint32_t bit_chk;
- uint32_t grp_calibrated;
- uint32_t write_group, write_test_bgn;
uint32_t failed_substage;
- debug("%s:%d: %u %u\n", __func__, __LINE__, read_group, test_bgn);
-
- /* update info for sims */
- reg_file_set_stage(CAL_STAGE_VFIFO);
-
- write_group = read_group;
- write_test_bgn = test_bgn;
-
- /* USER Determine number of delay taps for each phase tap */
- dtaps_per_ptap = 0;
- tmp_delay = 0;
- while (tmp_delay < IO_DELAY_PER_OPA_TAP) {
- dtaps_per_ptap++;
- tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
- }
- dtaps_per_ptap--;
- tmp_delay = 0;
+ int ret;
- /* update info for sims */
- reg_file_set_group(read_group);
-
- grp_calibrated = 0;
+ debug("%s:%d: %u %u\n", __func__, __LINE__, rw_group, test_bgn);
+ /* Update info for sims */
+ reg_file_set_group(rw_group);
+ reg_file_set_stage(CAL_STAGE_VFIFO);
reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
+
failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
- for (d = 0; d <= dtaps_per_ptap && grp_calibrated == 0; d += 2) {
+ /* USER Determine number of delay taps for each phase tap. */
+ dtaps_per_ptap = DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP,
+ IO_DELAY_PER_DQS_EN_DCHAIN_TAP) - 1;
+
+ for (d = 0; d <= dtaps_per_ptap; d += 2) {
/*
* In RLDRAMX we may be messing the delay of pins in
- * the same write group but outside of the current read
- * the group, but that's ok because we haven't
- * calibrated output side yet.
+ * the same write rw_group but outside of the current read
+ * the rw_group, but that's ok because we haven't calibrated
+ * output side yet.
*/
if (d > 0) {
- scc_mgr_apply_group_all_out_delay_add_all_ranks
- (write_group, write_test_bgn, d);
+ scc_mgr_apply_group_all_out_delay_add_all_ranks(
+ rw_group, d);
}
- for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX && grp_calibrated == 0;
- p++) {
- /* set a particular dqdqs phase */
- scc_mgr_set_dqdqs_output_phase_all_ranks(read_group, p);
+ for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX; p++) {
+ /* 1) Guaranteed Write */
+ ret = rw_mgr_mem_calibrate_guaranteed_write(rw_group, p);
+ if (ret)
+ break;
- debug_cond(DLEVEL == 1, "%s:%d calibrate_vfifo: g=%u \
- p=%u d=%u\n", __func__, __LINE__,
- read_group, p, d);
+ /* 2) DQS Enable Calibration */
+ ret = rw_mgr_mem_calibrate_dqs_enable_calibration(rw_group,
+ test_bgn);
+ if (ret) {
+ failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
+ continue;
+ }
+ /* 3) Centering DQ/DQS */
/*
- * Load up the patterns used by read calibration
- * using current DQDQS phase.
+ * If doing read after write calibration, do not update
+ * FOM now. Do it then.
*/
- rw_mgr_mem_calibrate_read_load_patterns(0, 1);
- if (!(gbl->phy_debug_mode_flags &
- PHY_DEBUG_DISABLE_GUARANTEED_READ)) {
- if (!rw_mgr_mem_calibrate_read_test_patterns_all_ranks
- (read_group, 1, &bit_chk)) {
- debug_cond(DLEVEL == 1, "%s:%d Guaranteed read test failed:",
- __func__, __LINE__);
- debug_cond(DLEVEL == 1, " g=%u p=%u d=%u\n",
- read_group, p, d);
- break;
- }
+ ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group,
+ test_bgn, 1, 0);
+ if (ret) {
+ failed_substage = CAL_SUBSTAGE_VFIFO_CENTER;
+ continue;
}
-/* case:56390 */
- grp_calibrated = 1;
- if (rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
- (write_group, read_group, test_bgn)) {
- /*
- * USER Read per-bit deskew can be done on a
- * per shadow register basis.
- */
- for (rank_bgn = 0, sr = 0;
- rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
- rank_bgn += NUM_RANKS_PER_SHADOW_REG,
- ++sr) {
- /*
- * Determine if this set of ranks
- * should be skipped entirely.
- */
- if (!param->skip_shadow_regs[sr]) {
- /*
- * If doing read after write
- * calibration, do not update
- * FOM, now - do it then.
- */
- if (!rw_mgr_mem_calibrate_vfifo_center
- (rank_bgn, write_group,
- read_group, test_bgn, 1, 0)) {
- grp_calibrated = 0;
- failed_substage =
- CAL_SUBSTAGE_VFIFO_CENTER;
- }
- }
- }
- } else {
- grp_calibrated = 0;
- failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
- }
+ /* All done. */
+ goto cal_done_ok;
}
}
- if (grp_calibrated == 0) {
- set_failing_group_stage(write_group, CAL_STAGE_VFIFO,
- failed_substage);
- return 0;
- }
+ /* Calibration Stage 1 failed. */
+ set_failing_group_stage(rw_group, CAL_STAGE_VFIFO, failed_substage);
+ return 0;
+ /* Calibration Stage 1 completed OK. */
+cal_done_ok:
/*
* Reset the delay chains back to zero if they have moved > 1
* (check for > 1 because loop will increase d even when pass in
* first case).
*/
if (d > 2)
- scc_mgr_zero_group(write_group, write_test_bgn, 1);
+ scc_mgr_zero_group(rw_group, 1);
return 1;
}
{
uint32_t found_one;
uint32_t bit_chk;
- uint32_t addr;
debug("%s:%d\n", __func__, __LINE__);
rw_mgr_mem_calibrate_read_load_patterns(0, 1);
found_one = 0;
- addr = sdr_get_addr(&phy_mgr_cfg->phy_rlat);
do {
- writel(gbl->curr_read_lat, SOCFPGA_SDR_ADDRESS + addr);
+ writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
__func__, __LINE__, gbl->curr_read_lat);
/* reset the fifos to get pointers to known state */
- addr = sdr_get_addr(&phy_mgr_cmd->fifo_reset);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &phy_mgr_cmd->fifo_reset);
if (found_one) {
/* add a fudge factor to the read latency that was determined */
gbl->curr_read_lat += 2;
- addr = sdr_get_addr(&phy_mgr_cfg->phy_rlat);
- writel(gbl->curr_read_lat, SOCFPGA_SDR_ADDRESS + addr);
+ writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \
read_lat=%u\n", __func__, __LINE__,
gbl->curr_read_lat);
* instruction that sends out the data. We set the counter to a
* large number so that the jump is always taken.
*/
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr2);
- writel(0xFF, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
/* CNTR 3 - Not used */
if (test_dm) {
mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add2);
writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
- SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add3);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
- SOCFPGA_SDR_ADDRESS + addr);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
} else {
mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add2);
- writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add3);
- writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
+ writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
}
} else if (rw_wl_nop_cycles == 0) {
/*
* to the DQS enable instruction. We set the counter to a large
* number so that the jump is always taken.
*/
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr2);
- writel(0xFF, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
/* CNTR 3 - Not used */
if (test_dm) {
mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add2);
writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
- SOCFPGA_SDR_ADDRESS + addr);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
} else {
mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add2);
- writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
}
} else {
/*
* and NOT take the jump. So we set the counter to 0. The jump
* address doesn't count.
*/
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr2);
- writel(0x0, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add2);
- writel(0x0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
+ writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
/*
* CNTR 3 - Set the nop counter to the number of cycles we
* need to loop for, minus 1.
*/
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr3);
- writel(rw_wl_nop_cycles - 1, SOCFPGA_SDR_ADDRESS + addr);
+ writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
if (test_dm) {
mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add3);
- writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
} else {
mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add3);
- writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
}
}
- addr = sdr_get_addr((u32 *)RW_MGR_RESET_READ_DATAPATH);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RESET_READ_DATAPATH_OFFSET);
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr0);
if (quick_write_mode)
- writel(0x08, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
else
- writel(0x40, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add0);
- writel(mcc_instruction, SOCFPGA_SDR_ADDRESS + addr);
+ writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
/*
* CNTR 1 - This is used to ensure enough time elapses
* for read data to come back.
*/
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr1);
- writel(0x30, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add1);
if (test_dm) {
- writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
} else {
- writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
}
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
- writel(mcc_instruction, SOCFPGA_SDR_ADDRESS + addr + (group << 2));
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
+ writel(mcc_instruction, addr + (group << 2));
}
/* Test writes, can check for a single bit pass or multiple bit pass */
uint32_t write_group, uint32_t use_dm, uint32_t all_correct,
uint32_t *bit_chk, uint32_t all_ranks)
{
- uint32_t addr;
uint32_t r;
uint32_t correct_mask_vg;
uint32_t tmp_bit_chk;
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
tmp_bit_chk = 0;
- addr = sdr_get_addr(&phy_mgr_cmd->fifo_reset);
addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
/* reset the fifos to get pointers to known state */
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &phy_mgr_cmd->fifo_reset);
tmp_bit_chk = tmp_bit_chk <<
(RW_MGR_MEM_DQ_PER_WRITE_DQS /
RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS+vg,
use_dm);
- base_rw_mgr = readl(SOCFPGA_SDR_ADDRESS + addr_rw_mgr);
+ base_rw_mgr = readl(addr_rw_mgr);
tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
if (vg == 0)
break;
dm_margin = 0;
- addr = sdr_get_addr((u32 *)SCC_MGR_IO_OUT1_DELAY);
- start_dqs = readl(SOCFPGA_SDR_ADDRESS + addr +
+ addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
+ start_dqs = readl(addr +
(RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
/* per-bit deskew */
}
/* Search for the left edge of the window for each bit */
- addr = (u32)&sdr_scc_mgr->update;
for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) {
- scc_mgr_apply_group_dq_out1_delay(write_group, test_bgn, d);
+ scc_mgr_apply_group_dq_out1_delay(write_group, d);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &sdr_scc_mgr->update);
/*
* Stop searching when the read test doesn't pass AND when
}
/* Reset DQ delay chains to 0 */
- scc_mgr_apply_group_dq_out1_delay(write_group, test_bgn, 0);
+ scc_mgr_apply_group_dq_out1_delay(0);
sticky_bit_chk = 0;
for (i = RW_MGR_MEM_DQ_PER_WRITE_DQS - 1;; i--) {
debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
}
/* Search for the right edge of the window for each bit */
- addr = (u32)&sdr_scc_mgr->update;
for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - start_dqs; d++) {
scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
d + start_dqs);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &sdr_scc_mgr->update);
/*
* Stop searching when the read test doesn't pass AND when
dq_margin = IO_IO_OUT1_DELAY_MAX + 1;
/* add delay to bring centre of all DQ windows to the same "level" */
- addr = sdr_get_addr((u32 *)SCC_MGR_IO_OUT1_DELAY);
for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
/* Use values before divide by 2 to reduce round off error */
shift_dq = (left_edge[i] - right_edge[i] -
debug_cond(DLEVEL == 2, "%s:%d write_center: before: shift_dq \
[%u]=%d\n", __func__, __LINE__, i, shift_dq);
- temp_dq_out1_delay = readl(SOCFPGA_SDR_ADDRESS + addr + (i << 2));
+ addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
+ temp_dq_out1_delay = readl(addr + (i << 2));
if (shift_dq + (int32_t)temp_dq_out1_delay >
(int32_t)IO_IO_OUT1_DELAY_MAX) {
shift_dq = (int32_t)IO_IO_OUT1_DELAY_MAX - temp_dq_out1_delay;
}
debug_cond(DLEVEL == 2, "write_center: after: shift_dq[%u]=%d\n",
i, shift_dq);
- scc_mgr_set_dq_out1_delay(write_group, i, temp_dq_out1_delay +
- shift_dq);
+ scc_mgr_set_dq_out1_delay(i, temp_dq_out1_delay + shift_dq);
scc_mgr_load_dq(i);
debug_cond(DLEVEL == 2, "write_center: margin[%u]=[%d,%d]\n", i,
/* Move DQS */
scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &sdr_scc_mgr->update);
/* Centre DM */
debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
int32_t win_best = 0;
/* Search for the/part of the window with DM shift */
- addr = (u32)&sdr_scc_mgr->update;
for (d = IO_IO_OUT1_DELAY_MAX; d >= 0; d -= DELTA_D) {
- scc_mgr_apply_group_dm_out1_delay(write_group, d);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ scc_mgr_apply_group_dm_out1_delay(d);
+ writel(0, &sdr_scc_mgr->update);
if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
PASS_ALL_BITS, &bit_chk,
/* Reset DM delay chains to 0 */
- scc_mgr_apply_group_dm_out1_delay(write_group, 0);
+ scc_mgr_apply_group_dm_out1_delay(0);
/*
* Check to see if the current window nudges up aganist 0 delay.
}
/* Search for the/part of the window with DQS shifts */
- addr = (u32)&sdr_scc_mgr->update;
for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - new_dqs; d += DELTA_D) {
/*
* Note: This only shifts DQS, so are we limiting ourselve to
scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
d + new_dqs);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &sdr_scc_mgr->update);
if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
PASS_ALL_BITS, &bit_chk,
0)) {
else
dm_margin = left_edge[0] - mid;
- scc_mgr_apply_group_dm_out1_delay(write_group, mid);
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ scc_mgr_apply_group_dm_out1_delay(mid);
+ writel(0, &sdr_scc_mgr->update);
debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
dm_margin=%d\n", __func__, __LINE__, left_edge[0],
* Do not remove this line as it makes sure all of our
* decisions have been applied.
*/
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &sdr_scc_mgr->update);
return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
}
return 1;
}
-/* precharge all banks and activate row 0 in bank "000..." and bank "111..." */
+/**
+ * mem_precharge_and_activate() - Precharge all banks and activate
+ *
+ * Precharge all banks and activate row 0 in bank "000..." and bank "111...".
+ */
static void mem_precharge_and_activate(void)
{
- uint32_t r;
- uint32_t addr;
+ int r;
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
- if (param->skip_ranks[r]) {
- /* request to skip the rank */
+ /* Test if the rank should be skipped. */
+ if (param->skip_ranks[r])
continue;
- }
- /* set rank */
+ /* Set rank. */
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
- /* precharge all banks ... */
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
- writel(RW_MGR_PRECHARGE_ALL, SOCFPGA_SDR_ADDRESS + addr);
+ /* Precharge all banks. */
+ writel(RW_MGR_PRECHARGE_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET);
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr0);
- writel(0x0F, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add0);
- writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
+ writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add0);
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr1);
- writel(0x0F, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add1);
- writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
+ writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
- /* activate rows */
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
- writel(RW_MGR_ACTIVATE_0_AND_1, SOCFPGA_SDR_ADDRESS + addr);
+ /* Activate rows. */
+ writel(RW_MGR_ACTIVATE_0_AND_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET);
}
}
-/* Configure various memory related parameters. */
-static void mem_config(void)
+/**
+ * mem_init_latency() - Configure memory RLAT and WLAT settings
+ *
+ * Configure memory RLAT and WLAT parameters.
+ */
+static void mem_init_latency(void)
{
- uint32_t rlat, wlat;
- uint32_t rw_wl_nop_cycles;
- uint32_t max_latency;
- uint32_t addr;
-
- debug("%s:%d\n", __func__, __LINE__);
- /* read in write and read latency */
- addr = sdr_get_addr(&data_mgr->t_wl_add);
- wlat = readl(SOCFPGA_SDR_ADDRESS + addr);
-
- addr = sdr_get_addr(&data_mgr->mem_t_add);
- wlat += readl(SOCFPGA_SDR_ADDRESS + addr);
- /* WL for hard phy does not include additive latency */
-
/*
- * add addtional write latency to offset the address/command extra
- * clock cycle. We change the AC mux setting causing AC to be delayed
- * by one mem clock cycle. Only do this for DDR3
+ * For AV/CV, LFIFO is hardened and always runs at full rate
+ * so max latency in AFI clocks, used here, is correspondingly
+ * smaller.
*/
- wlat = wlat + 1;
+ const u32 max_latency = (1 << MAX_LATENCY_COUNT_WIDTH) - 1;
+ u32 rlat, wlat;
- addr = sdr_get_addr(&data_mgr->t_rl_add);
- rlat = readl(SOCFPGA_SDR_ADDRESS + addr);
-
- rw_wl_nop_cycles = wlat - 2;
- gbl->rw_wl_nop_cycles = rw_wl_nop_cycles;
+ debug("%s:%d\n", __func__, __LINE__);
/*
- * For AV/CV, lfifo is hardened and always runs at full rate so
- * max latency in AFI clocks, used here, is correspondingly smaller.
+ * Read in write latency.
+ * WL for Hard PHY does not include additive latency.
*/
- max_latency = (1<<MAX_LATENCY_COUNT_WIDTH)/1 - 1;
- /* configure for a burst length of 8 */
+ wlat = readl(&data_mgr->t_wl_add);
+ wlat += readl(&data_mgr->mem_t_add);
- /* write latency */
- /* Adjust Write Latency for Hard PHY */
- wlat = wlat + 1;
+ gbl->rw_wl_nop_cycles = wlat - 1;
- /* set a pretty high read latency initially */
- gbl->curr_read_lat = rlat + 16;
+ /* Read in readl latency. */
+ rlat = readl(&data_mgr->t_rl_add);
+ /* Set a pretty high read latency initially. */
+ gbl->curr_read_lat = rlat + 16;
if (gbl->curr_read_lat > max_latency)
gbl->curr_read_lat = max_latency;
- addr = sdr_get_addr(&phy_mgr_cfg->phy_rlat);
- writel(gbl->curr_read_lat, SOCFPGA_SDR_ADDRESS + addr);
+ writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
- /* advertise write latency */
- gbl->curr_write_lat = wlat;
- addr = sdr_get_addr(&phy_mgr_cfg->afi_wlat);
- writel(wlat - 2, SOCFPGA_SDR_ADDRESS + addr);
-
- /* initialize bit slips */
- mem_precharge_and_activate();
+ /* Advertise write latency. */
+ writel(wlat, &phy_mgr_cfg->afi_wlat);
}
-/* Set VFIFO and LFIFO to instant-on settings in skip calibration mode */
+/**
+ * @mem_skip_calibrate() - Set VFIFO and LFIFO to instant-on settings
+ *
+ * Set VFIFO and LFIFO to instant-on settings in skip calibration mode.
+ */
static void mem_skip_calibrate(void)
{
uint32_t vfifo_offset;
uint32_t i, j, r;
- uint32_t addr;
debug("%s:%d\n", __func__, __LINE__);
/* Need to update every shadow register set used by the interface */
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
- r += NUM_RANKS_PER_SHADOW_REG) {
+ r += NUM_RANKS_PER_SHADOW_REG) {
/*
* Set output phase alignment settings appropriate for
* skip calibration.
*
* (1.25 * IO_DLL_CHAIN_LENGTH - 2)
*/
- scc_mgr_set_dqdqs_output_phase(i, (1.25 *
- IO_DLL_CHAIN_LENGTH - 2));
+ scc_mgr_set_dqdqs_output_phase(i,
+ 1.25 * IO_DLL_CHAIN_LENGTH - 2);
}
- addr = (u32)&sdr_scc_mgr->dqs_ena;
- writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
- addr = (u32)&sdr_scc_mgr->dqs_io_ena;
- writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0xff, &sdr_scc_mgr->dqs_ena);
+ writel(0xff, &sdr_scc_mgr->dqs_io_ena);
- addr = sdr_get_addr((u32 *)SCC_MGR_GROUP_COUNTER);
for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
- writel(i, SOCFPGA_SDR_ADDRESS + addr);
+ writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
+ SCC_MGR_GROUP_COUNTER_OFFSET);
}
- addr = (u32)&sdr_scc_mgr->dq_ena;
- writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
- addr = (u32)&sdr_scc_mgr->dm_ena;
- writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0xff, &sdr_scc_mgr->dq_ena);
+ writel(0xff, &sdr_scc_mgr->dm_ena);
+ writel(0, &sdr_scc_mgr->update);
}
/* Compensate for simulation model behaviour */
scc_mgr_set_dqs_bus_in_delay(i, 10);
scc_mgr_load_dqs(i);
}
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &sdr_scc_mgr->update);
/*
* ArriaV has hard FIFOs that can only be initialized by incrementing
* in sequencer.
*/
vfifo_offset = CALIB_VFIFO_OFFSET;
- addr = sdr_get_addr(&phy_mgr_cmd->inc_vfifo_hard_phy);
- for (j = 0; j < vfifo_offset; j++) {
- writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
- }
- addr = sdr_get_addr(&phy_mgr_cmd->fifo_reset);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ for (j = 0; j < vfifo_offset; j++)
+ writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
+ writel(0, &phy_mgr_cmd->fifo_reset);
/*
- * For ACV with hard lfifo, we get the skip-cal setting from
- * generation-time constant.
+ * For Arria V and Cyclone V with hard LFIFO, we get the skip-cal
+ * setting from generation-time constant.
*/
gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
- addr = sdr_get_addr(&phy_mgr_cfg->phy_rlat);
- writel(gbl->curr_read_lat, SOCFPGA_SDR_ADDRESS + addr);
+ writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
}
-/* Memory calibration entry point */
+/**
+ * mem_calibrate() - Memory calibration entry point.
+ *
+ * Perform memory calibration.
+ */
static uint32_t mem_calibrate(void)
{
uint32_t i;
uint32_t run_groups, current_run;
uint32_t failing_groups = 0;
uint32_t group_failed = 0;
- uint32_t sr_failed = 0;
- uint32_t addr;
+
+ const u32 rwdqs_ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
+ RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
debug("%s:%d\n", __func__, __LINE__);
- /* Initialize the data settings */
+ /* Initialize the data settings */
gbl->error_substage = CAL_SUBSTAGE_NIL;
gbl->error_stage = CAL_STAGE_NIL;
gbl->error_group = 0xff;
gbl->fom_in = 0;
gbl->fom_out = 0;
- mem_config();
+ /* Initialize WLAT and RLAT. */
+ mem_init_latency();
+
+ /* Initialize bit slips. */
+ mem_precharge_and_activate();
- uint32_t bypass_mode = 0x1;
- addr = sdr_get_addr((u32 *)SCC_MGR_GROUP_COUNTER);
for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
- writel(i, SOCFPGA_SDR_ADDRESS + addr);
- scc_set_bypass_mode(i, bypass_mode);
+ writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
+ SCC_MGR_GROUP_COUNTER_OFFSET);
+ /* Only needed once to set all groups, pins, DQ, DQS, DM. */
+ if (i == 0)
+ scc_mgr_set_hhp_extras();
+
+ scc_set_bypass_mode(i);
}
+ /* Calibration is skipped. */
if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
/*
* Set VFIFO and LFIFO to instant-on settings in skip
* calibration mode.
*/
mem_skip_calibrate();
- } else {
- for (i = 0; i < NUM_CALIB_REPEAT; i++) {
- /*
- * Zero all delay chain/phase settings for all
- * groups and all shadow register sets.
- */
- scc_mgr_zero_all();
- run_groups = ~param->skip_groups;
+ /*
+ * Do not remove this line as it makes sure all of our
+ * decisions have been applied.
+ */
+ writel(0, &sdr_scc_mgr->update);
+ return 1;
+ }
- for (write_group = 0, write_test_bgn = 0; write_group
- < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++,
- write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) {
- /* Initialized the group failure */
- group_failed = 0;
+ /* Calibration is not skipped. */
+ for (i = 0; i < NUM_CALIB_REPEAT; i++) {
+ /*
+ * Zero all delay chain/phase settings for all
+ * groups and all shadow register sets.
+ */
+ scc_mgr_zero_all();
- current_run = run_groups & ((1 <<
- RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
- run_groups = run_groups >>
- RW_MGR_NUM_DQS_PER_WRITE_GROUP;
+ run_groups = ~param->skip_groups;
- if (current_run == 0)
- continue;
+ for (write_group = 0, write_test_bgn = 0; write_group
+ < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++,
+ write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) {
- addr = sdr_get_addr((u32 *)SCC_MGR_GROUP_COUNTER);
- writel(write_group, SOCFPGA_SDR_ADDRESS + addr);
- scc_mgr_zero_group(write_group, write_test_bgn,
- 0);
+ /* Initialize the group failure */
+ group_failed = 0;
- for (read_group = write_group *
- RW_MGR_MEM_IF_READ_DQS_WIDTH /
- RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
- read_test_bgn = 0;
- read_group < (write_group + 1) *
- RW_MGR_MEM_IF_READ_DQS_WIDTH /
- RW_MGR_MEM_IF_WRITE_DQS_WIDTH &&
- group_failed == 0;
- read_group++, read_test_bgn +=
- RW_MGR_MEM_DQ_PER_READ_DQS) {
- /* Calibrate the VFIFO */
- if (!((STATIC_CALIB_STEPS) &
- CALIB_SKIP_VFIFO)) {
- if (!rw_mgr_mem_calibrate_vfifo
- (read_group,
- read_test_bgn)) {
- group_failed = 1;
-
- if (!(gbl->
- phy_debug_mode_flags &
- PHY_DEBUG_SWEEP_ALL_GROUPS)) {
- return 0;
- }
- }
- }
- }
+ current_run = run_groups & ((1 <<
+ RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
+ run_groups = run_groups >>
+ RW_MGR_NUM_DQS_PER_WRITE_GROUP;
- /* Calibrate the output side */
- if (group_failed == 0) {
- for (rank_bgn = 0, sr = 0; rank_bgn
- < RW_MGR_MEM_NUMBER_OF_RANKS;
- rank_bgn +=
- NUM_RANKS_PER_SHADOW_REG,
- ++sr) {
- sr_failed = 0;
- if (!((STATIC_CALIB_STEPS) &
- CALIB_SKIP_WRITES)) {
- if ((STATIC_CALIB_STEPS)
- & CALIB_SKIP_DELAY_SWEEPS) {
- /* not needed in quick mode! */
- } else {
- /*
- * Determine if this set of
- * ranks should be skipped
- * entirely.
- */
- if (!param->skip_shadow_regs[sr]) {
- if (!rw_mgr_mem_calibrate_writes
- (rank_bgn, write_group,
- write_test_bgn)) {
- sr_failed = 1;
- if (!(gbl->
- phy_debug_mode_flags &
- PHY_DEBUG_SWEEP_ALL_GROUPS)) {
- return 0;
- }
- }
- }
- }
- }
- if (sr_failed != 0)
- group_failed = 1;
- }
- }
+ if (current_run == 0)
+ continue;
- if (group_failed == 0) {
- for (read_group = write_group *
- RW_MGR_MEM_IF_READ_DQS_WIDTH /
- RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
- read_test_bgn = 0;
- read_group < (write_group + 1)
- * RW_MGR_MEM_IF_READ_DQS_WIDTH
- / RW_MGR_MEM_IF_WRITE_DQS_WIDTH &&
- group_failed == 0;
- read_group++, read_test_bgn +=
- RW_MGR_MEM_DQ_PER_READ_DQS) {
- if (!((STATIC_CALIB_STEPS) &
- CALIB_SKIP_WRITES)) {
- if (!rw_mgr_mem_calibrate_vfifo_end
- (read_group, read_test_bgn)) {
- group_failed = 1;
-
- if (!(gbl->phy_debug_mode_flags
- & PHY_DEBUG_SWEEP_ALL_GROUPS)) {
- return 0;
- }
- }
- }
- }
- }
+ writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
+ SCC_MGR_GROUP_COUNTER_OFFSET);
+ scc_mgr_zero_group(write_group, 0);
+
+ for (read_group = write_group * rwdqs_ratio,
+ read_test_bgn = 0;
+ read_group < (write_group + 1) * rwdqs_ratio;
+ read_group++,
+ read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
+ if (STATIC_CALIB_STEPS & CALIB_SKIP_VFIFO)
+ continue;
+
+ /* Calibrate the VFIFO */
+ if (rw_mgr_mem_calibrate_vfifo(read_group,
+ read_test_bgn))
+ continue;
+
+ if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
+ return 0;
- if (group_failed != 0)
- failing_groups++;
+ /* The group failed, we're done. */
+ goto grp_failed;
}
- /*
- * USER If there are any failing groups then report
- * the failure.
- */
- if (failing_groups != 0)
- return 0;
+ /* Calibrate the output side */
+ for (rank_bgn = 0, sr = 0;
+ rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
+ rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
+ if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
+ continue;
+
+ /* Not needed in quick mode! */
+ if (STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS)
+ continue;
- /* Calibrate the LFIFO */
- if (!((STATIC_CALIB_STEPS) & CALIB_SKIP_LFIFO)) {
/*
- * If we're skipping groups as part of debug,
- * don't calibrate LFIFO.
+ * Determine if this set of ranks
+ * should be skipped entirely.
*/
- if (param->skip_groups == 0) {
- if (!rw_mgr_mem_calibrate_lfifo())
- return 0;
- }
+ if (param->skip_shadow_regs[sr])
+ continue;
+
+ /* Calibrate WRITEs */
+ if (rw_mgr_mem_calibrate_writes(rank_bgn,
+ write_group, write_test_bgn))
+ continue;
+
+ group_failed = 1;
+ if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
+ return 0;
+ }
+
+ /* Some group failed, we're done. */
+ if (group_failed)
+ goto grp_failed;
+
+ for (read_group = write_group * rwdqs_ratio,
+ read_test_bgn = 0;
+ read_group < (write_group + 1) * rwdqs_ratio;
+ read_group++,
+ read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
+ if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
+ continue;
+
+ if (rw_mgr_mem_calibrate_vfifo_end(read_group,
+ read_test_bgn))
+ continue;
+
+ if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
+ return 0;
+
+ /* The group failed, we're done. */
+ goto grp_failed;
}
+
+ /* No group failed, continue as usual. */
+ continue;
+
+grp_failed: /* A group failed, increment the counter. */
+ failing_groups++;
}
+
+ /*
+ * USER If there are any failing groups then report
+ * the failure.
+ */
+ if (failing_groups != 0)
+ return 0;
+
+ if (STATIC_CALIB_STEPS & CALIB_SKIP_LFIFO)
+ continue;
+
+ /*
+ * If we're skipping groups as part of debug,
+ * don't calibrate LFIFO.
+ */
+ if (param->skip_groups != 0)
+ continue;
+
+ /* Calibrate the LFIFO */
+ if (!rw_mgr_mem_calibrate_lfifo())
+ return 0;
}
/*
* Do not remove this line as it makes sure all of our decisions
* have been applied.
*/
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &sdr_scc_mgr->update);
return 1;
}
-static uint32_t run_mem_calibrate(void)
+/**
+ * run_mem_calibrate() - Perform memory calibration
+ *
+ * This function triggers the entire memory calibration procedure.
+ */
+static int run_mem_calibrate(void)
{
- uint32_t pass;
- uint32_t debug_info;
- uint32_t addr;
+ int pass;
debug("%s:%d\n", __func__, __LINE__);
/* Reset pass/fail status shown on afi_cal_success/fail */
- addr = sdr_get_addr(&phy_mgr_cfg->cal_status);
- writel(PHY_MGR_CAL_RESET, SOCFPGA_SDR_ADDRESS + addr);
-
- addr = sdr_get_addr((u32 *)BASE_MMR);
- /* stop tracking manger */
- uint32_t ctrlcfg = readl(SOCFPGA_SDR_ADDRESS + addr);
+ writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
- addr = sdr_get_addr((u32 *)BASE_MMR);
- writel(ctrlcfg & 0xFFBFFFFF, SOCFPGA_SDR_ADDRESS + addr);
+ /* Stop tracking manager. */
+ clrbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
- initialize();
+ phy_mgr_initialize();
rw_mgr_mem_initialize();
+ /* Perform the actual memory calibration. */
pass = mem_calibrate();
mem_precharge_and_activate();
- addr = sdr_get_addr(&phy_mgr_cmd->fifo_reset);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &phy_mgr_cmd->fifo_reset);
+ /* Handoff. */
+ rw_mgr_mem_handoff();
/*
- * Handoff:
- * Don't return control of the PHY back to AFI when in debug mode.
+ * In Hard PHY this is a 2-bit control:
+ * 0: AFI Mux Select
+ * 1: DDIO Mux Select
*/
- if ((gbl->phy_debug_mode_flags & PHY_DEBUG_IN_DEBUG_MODE) == 0) {
- rw_mgr_mem_handoff();
- /*
- * In Hard PHY this is a 2-bit control:
- * 0: AFI Mux Select
- * 1: DDIO Mux Select
- */
- addr = sdr_get_addr(&phy_mgr_cfg->mux_sel);
- writel(0x2, SOCFPGA_SDR_ADDRESS + addr);
- }
+ writel(0x2, &phy_mgr_cfg->mux_sel);
+
+ /* Start tracking manager. */
+ setbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
+
+ return pass;
+}
- addr = sdr_get_addr((u32 *)BASE_MMR);
- writel(ctrlcfg, SOCFPGA_SDR_ADDRESS + addr);
+/**
+ * debug_mem_calibrate() - Report result of memory calibration
+ * @pass: Value indicating whether calibration passed or failed
+ *
+ * This function reports the results of the memory calibration
+ * and writes debug information into the register file.
+ */
+static void debug_mem_calibrate(int pass)
+{
+ uint32_t debug_info;
if (pass) {
printf("%s: CALIBRATION PASSED\n", __FILE__);
/* Update the FOM in the register file */
debug_info = gbl->fom_in;
debug_info |= gbl->fom_out << 8;
- addr = (u32)&sdr_reg_file->fom;
- writel(debug_info, SOCFPGA_SDR_ADDRESS + addr);
+ writel(debug_info, &sdr_reg_file->fom);
- addr = sdr_get_addr(&phy_mgr_cfg->cal_debug_info);
- writel(debug_info, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&phy_mgr_cfg->cal_status);
- writel(PHY_MGR_CAL_SUCCESS, SOCFPGA_SDR_ADDRESS + addr);
+ writel(debug_info, &phy_mgr_cfg->cal_debug_info);
+ writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
} else {
printf("%s: CALIBRATION FAILED\n", __FILE__);
debug_info |= gbl->error_substage << 8;
debug_info |= gbl->error_group << 16;
- addr = (u32)&sdr_reg_file->failing_stage;
- writel(debug_info, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&phy_mgr_cfg->cal_debug_info);
- writel(debug_info, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&phy_mgr_cfg->cal_status);
- writel(PHY_MGR_CAL_FAIL, SOCFPGA_SDR_ADDRESS + addr);
+ writel(debug_info, &sdr_reg_file->failing_stage);
+ writel(debug_info, &phy_mgr_cfg->cal_debug_info);
+ writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status);
/* Update the failing group/stage in the register file */
debug_info = gbl->error_stage;
debug_info |= gbl->error_substage << 8;
debug_info |= gbl->error_group << 16;
- addr = (u32)&sdr_reg_file->failing_stage;
- writel(debug_info, SOCFPGA_SDR_ADDRESS + addr);
+ writel(debug_info, &sdr_reg_file->failing_stage);
}
- return pass;
+ printf("%s: Calibration complete\n", __FILE__);
}
+/**
+ * hc_initialize_rom_data() - Initialize ROM data
+ *
+ * Initialize ROM data.
+ */
static void hc_initialize_rom_data(void)
{
- uint32_t i;
- uint32_t addr;
+ u32 i, addr;
- addr = sdr_get_addr((u32 *)(RW_MGR_INST_ROM_WRITE));
- for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++) {
- uint32_t data = inst_rom_init[i];
- writel(data, SOCFPGA_SDR_ADDRESS + addr + (i << 2));
- }
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
+ for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++)
+ writel(inst_rom_init[i], addr + (i << 2));
- addr = sdr_get_addr((u32 *)(RW_MGR_AC_ROM_WRITE));
- for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++) {
- uint32_t data = ac_rom_init[i];
- writel(data, SOCFPGA_SDR_ADDRESS + addr + (i << 2));
- }
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
+ for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++)
+ writel(ac_rom_init[i], addr + (i << 2));
}
+/**
+ * initialize_reg_file() - Initialize SDR register file
+ *
+ * Initialize SDR register file.
+ */
static void initialize_reg_file(void)
{
- uint32_t addr;
-
/* Initialize the register file with the correct data */
- addr = (u32)&sdr_reg_file->signature;
- writel(REG_FILE_INIT_SEQ_SIGNATURE, SOCFPGA_SDR_ADDRESS + addr);
-
- addr = (u32)&sdr_reg_file->debug_data_addr;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
-
- addr = (u32)&sdr_reg_file->cur_stage;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
-
- addr = (u32)&sdr_reg_file->fom;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
-
- addr = (u32)&sdr_reg_file->failing_stage;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
-
- addr = (u32)&sdr_reg_file->debug1;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
-
- addr = (u32)&sdr_reg_file->debug2;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(REG_FILE_INIT_SEQ_SIGNATURE, &sdr_reg_file->signature);
+ writel(0, &sdr_reg_file->debug_data_addr);
+ writel(0, &sdr_reg_file->cur_stage);
+ writel(0, &sdr_reg_file->fom);
+ writel(0, &sdr_reg_file->failing_stage);
+ writel(0, &sdr_reg_file->debug1);
+ writel(0, &sdr_reg_file->debug2);
}
+/**
+ * initialize_hps_phy() - Initialize HPS PHY
+ *
+ * Initialize HPS PHY.
+ */
static void initialize_hps_phy(void)
{
uint32_t reg;
- uint32_t addr;
/*
* Tracking also gets configured here because it's in the
* same register.
reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
trk_sample_count);
- addr = sdr_get_addr((u32 *)BASE_MMR);
- writel(reg, SOCFPGA_SDR_ADDRESS + addr + SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_OFFSET);
+ writel(reg, &sdr_ctrl->phy_ctrl0);
reg = 0;
reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
trk_long_idle_sample_count);
- writel(reg, SOCFPGA_SDR_ADDRESS + addr + SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_OFFSET);
+ writel(reg, &sdr_ctrl->phy_ctrl1);
reg = 0;
reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
trk_long_idle_sample_count >>
SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
- writel(reg, SOCFPGA_SDR_ADDRESS + addr + SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_OFFSET);
+ writel(reg, &sdr_ctrl->phy_ctrl2);
}
+/**
+ * initialize_tracking() - Initialize tracking
+ *
+ * Initialize the register file with usable initial data.
+ */
static void initialize_tracking(void)
{
- uint32_t concatenated_longidle = 0x0;
- uint32_t concatenated_delays = 0x0;
- uint32_t concatenated_rw_addr = 0x0;
- uint32_t concatenated_refresh = 0x0;
- uint32_t trk_sample_count = 7500;
- uint32_t dtaps_per_ptap;
- uint32_t tmp_delay;
- uint32_t addr;
-
/*
- * compute usable version of value in case we skip full
- * computation later
+ * Initialize the register file with the correct data.
+ * Compute usable version of value in case we skip full
+ * computation later.
*/
- dtaps_per_ptap = 0;
- tmp_delay = 0;
- while (tmp_delay < IO_DELAY_PER_OPA_TAP) {
- dtaps_per_ptap++;
- tmp_delay += IO_DELAY_PER_DCHAIN_TAP;
- }
- dtaps_per_ptap--;
-
- concatenated_longidle = concatenated_longidle ^ 10;
- /*longidle outer loop */
- concatenated_longidle = concatenated_longidle << 16;
- concatenated_longidle = concatenated_longidle ^ 100;
- /*longidle sample count */
- concatenated_delays = concatenated_delays ^ 243;
- /* trfc, worst case of 933Mhz 4Gb */
- concatenated_delays = concatenated_delays << 8;
- concatenated_delays = concatenated_delays ^ 14;
- /* trcd, worst case */
- concatenated_delays = concatenated_delays << 8;
- concatenated_delays = concatenated_delays ^ 10;
- /* vfifo wait */
- concatenated_delays = concatenated_delays << 8;
- concatenated_delays = concatenated_delays ^ 4;
- /* mux delay */
-
- concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_IDLE;
- concatenated_rw_addr = concatenated_rw_addr << 8;
- concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_ACTIVATE_1;
- concatenated_rw_addr = concatenated_rw_addr << 8;
- concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_SGLE_READ;
- concatenated_rw_addr = concatenated_rw_addr << 8;
- concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_PRECHARGE_ALL;
-
- concatenated_refresh = concatenated_refresh ^ RW_MGR_REFRESH_ALL;
- concatenated_refresh = concatenated_refresh << 24;
- concatenated_refresh = concatenated_refresh ^ 1000; /* trefi */
-
- /* Initialize the register file with the correct data */
- addr = (u32)&sdr_reg_file->dtaps_per_ptap;
- writel(dtaps_per_ptap, SOCFPGA_SDR_ADDRESS + addr);
+ writel(DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP) - 1,
+ &sdr_reg_file->dtaps_per_ptap);
- addr = (u32)&sdr_reg_file->trk_sample_count;
- writel(trk_sample_count, SOCFPGA_SDR_ADDRESS + addr);
+ /* trk_sample_count */
+ writel(7500, &sdr_reg_file->trk_sample_count);
- addr = (u32)&sdr_reg_file->trk_longidle;
- writel(concatenated_longidle, SOCFPGA_SDR_ADDRESS + addr);
+ /* longidle outer loop [15:0] */
+ writel((10 << 16) | (100 << 0), &sdr_reg_file->trk_longidle);
- addr = (u32)&sdr_reg_file->delays;
- writel(concatenated_delays, SOCFPGA_SDR_ADDRESS + addr);
+ /*
+ * longidle sample count [31:24]
+ * trfc, worst case of 933Mhz 4Gb [23:16]
+ * trcd, worst case [15:8]
+ * vfifo wait [7:0]
+ */
+ writel((243 << 24) | (14 << 16) | (10 << 8) | (4 << 0),
+ &sdr_reg_file->delays);
- addr = (u32)&sdr_reg_file->trk_rw_mgr_addr;
- writel(concatenated_rw_addr, SOCFPGA_SDR_ADDRESS + addr);
+ /* mux delay */
+ writel((RW_MGR_IDLE << 24) | (RW_MGR_ACTIVATE_1 << 16) |
+ (RW_MGR_SGLE_READ << 8) | (RW_MGR_PRECHARGE_ALL << 0),
+ &sdr_reg_file->trk_rw_mgr_addr);
- addr = (u32)&sdr_reg_file->trk_read_dqs_width;
- writel(RW_MGR_MEM_IF_READ_DQS_WIDTH, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MEM_IF_READ_DQS_WIDTH,
+ &sdr_reg_file->trk_read_dqs_width);
- addr = (u32)&sdr_reg_file->trk_rfsh;
- writel(concatenated_refresh, SOCFPGA_SDR_ADDRESS + addr);
+ /* trefi [7:0] */
+ writel((RW_MGR_REFRESH_ALL << 24) | (1000 << 0),
+ &sdr_reg_file->trk_rfsh);
}
int sdram_calibration_full(void)
struct param_type my_param;
struct gbl_type my_gbl;
uint32_t pass;
- uint32_t i;
+
+ memset(&my_param, 0, sizeof(my_param));
+ memset(&my_gbl, 0, sizeof(my_gbl));
param = &my_param;
gbl = &my_gbl;
- /* Initialize the debug mode flags */
- gbl->phy_debug_mode_flags = 0;
/* Set the calibration enabled by default */
gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
/*
initialize_tracking();
- /* USER Enable all ranks, groups */
- for (i = 0; i < RW_MGR_MEM_NUMBER_OF_RANKS; i++)
- param->skip_ranks[i] = 0;
- for (i = 0; i < NUM_SHADOW_REGS; ++i)
- param->skip_shadow_regs[i] = 0;
- param->skip_groups = 0;
-
printf("%s: Preparing to start memory calibration\n", __FILE__);
debug("%s:%d\n", __func__, __LINE__);
skip_delay_mask = 0x0;
pass = run_mem_calibrate();
-
- printf("%s: Calibration complete\n", __FILE__);
+ debug_mem_calibrate(pass);
return pass;
}
projects / people / ms / u-boot.git / blobdiff