Merge drm/drm-next into drm-intel-next

[people/ms/linux.git] / drivers / gpu / drm / i915 / gt / intel_rc6.c

diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index c3155ee5868923dcbb0e522f86a3447a19c37fd2..bb0d6e363f5d1920cccb5053938feb67636e735c 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -7,6 +7,7 @@
 
 #include "i915_drv.h"
 #include "i915_vgpu.h"
+#include "intel_engine_regs.h"
 #include "intel_gt.h"
 #include "intel_gt_pm.h"
 #include "intel_pcode.h"
@@ -267,8 +268,7 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6)
            GEN6_RC_CTL_HW_ENABLE;
 
        rc6vids = 0;
-       ret = sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,
-                                    &rc6vids, NULL);
+       ret = snb_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL);
        if (GRAPHICS_VER(i915) == 6 && ret) {
                drm_dbg(&i915->drm, "Couldn't check for BIOS workaround\n");
        } else if (GRAPHICS_VER(i915) == 6 &&
@@ -278,7 +278,7 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6)
                        GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
                rc6vids &= 0xffff00;
                rc6vids |= GEN6_ENCODE_RC6_VID(450);
-               ret = sandybridge_pcode_write(i915, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
+               ret = snb_pcode_write(i915, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
                if (ret)
                        drm_err(&i915->drm,
                                "Couldn't fix incorrect rc6 voltage\n");
@@ -449,10 +449,10 @@ static bool bxt_check_bios_rc6_setup(struct intel_rc6 *rc6)
                enable_rc6 = false;
        }
 
-       if (!((intel_uncore_read(uncore, PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1 &&
-             (intel_uncore_read(uncore, PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1 &&
-             (intel_uncore_read(uncore, PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1 &&
-             (intel_uncore_read(uncore, PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1)) {
+       if (!((intel_uncore_read(uncore, PWRCTX_MAXCNT(RENDER_RING_BASE)) & IDLE_TIME_MASK) > 1 &&
+             (intel_uncore_read(uncore, PWRCTX_MAXCNT(GEN6_BSD_RING_BASE)) & IDLE_TIME_MASK) > 1 &&
+             (intel_uncore_read(uncore, PWRCTX_MAXCNT(BLT_RING_BASE)) & IDLE_TIME_MASK) > 1 &&
+             (intel_uncore_read(uncore, PWRCTX_MAXCNT(VEBOX_RING_BASE)) & IDLE_TIME_MASK) > 1)) {
                drm_dbg(&i915->drm,
                        "Engine Idle wait time not set properly.\n");
                enable_rc6 = false;