Merge tag 'drm-intel-next-2022-06-22' of git://anongit.freedesktop.org/drm/drm-intel...

[thirdparty/kernel/linux.git] / drivers / gpu / drm / i915 / i915_reg.h

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cc608e264e23e6e7ded944f97ef90471fc061cc5..616164fa2e320ed1e5f36ca8b09182225dd79c1f 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -976,6 +976,10 @@
 #define GEN12_COMPUTE2_RING_BASE       0x1e000
 #define GEN12_COMPUTE3_RING_BASE       0x26000
 #define BLT_RING_BASE          0x22000
+#define DG1_GSC_HECI1_BASE     0x00258000
+#define DG1_GSC_HECI2_BASE     0x00259000
+#define DG2_GSC_HECI1_BASE     0x00373000
+#define DG2_GSC_HECI2_BASE     0x00374000
 
 
 
@@ -1843,6 +1847,17 @@
 #define GEN9_RP_STATE_LIMITS   _MMIO(0x138148)
 #define XEHPSDV_RP_STATE_CAP   _MMIO(0x250014)
 
+#define GT0_PERF_LIMIT_REASONS         _MMIO(0x1381a8)
+#define   GT0_PERF_LIMIT_REASONS_MASK  0xde3
+#define   PROCHOT_MASK                 REG_BIT(1)
+#define   THERMAL_LIMIT_MASK           REG_BIT(2)
+#define   RATL_MASK                    REG_BIT(6)
+#define   VR_THERMALERT_MASK           REG_BIT(7)
+#define   VR_TDC_MASK                  REG_BIT(8)
+#define   POWER_LIMIT_4_MASK           REG_BIT(9)
+#define   POWER_LIMIT_1_MASK           REG_BIT(11)
+#define   POWER_LIMIT_2_MASK           REG_BIT(12)
+
 #define CHV_CLK_CTL1                   _MMIO(0x101100)
 #define VLV_CLK_CTL2                   _MMIO(0x101104)
 #define   CLK_CTL2_CZCOUNT_30NS_SHIFT  28
@@ -8313,6 +8328,9 @@ enum skl_power_gate {
 #define   SGGI_DIS                     REG_BIT(15)
 #define   SGR_DIS                      REG_BIT(13)
 
+#define XEHPSDV_TILE0_ADDR_RANGE       _MMIO(0x4900)
+#define   XEHPSDV_TILE_LMEM_RANGE_SHIFT  8
+
 #define XEHPSDV_FLAT_CCS_BASE_ADDR     _MMIO(0x4910)
 #define   XEHPSDV_CCS_BASE_SHIFT       8