*/
#include <common.h>
+#include <errno.h>
#include <malloc.h>
#include <mmc.h>
#include <sdhci.h>
unsigned int start_addr)
{
unsigned int stat, rdy, mask, timeout, block = 0;
-#ifdef CONFIG_MMC_SDMA
+ bool transfer_done = false;
+#ifdef CONFIG_MMC_SDHCI_SDMA
unsigned char ctrl;
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
ctrl &= ~SDHCI_CTRL_DMA_MASK;
if (stat & SDHCI_INT_ERROR) {
printf("%s: Error detected in status(0x%X)!\n",
__func__, stat);
- return -1;
+ return -EIO;
}
- if (stat & rdy) {
+ if (!transfer_done && (stat & rdy)) {
if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
continue;
sdhci_writel(host, rdy, SDHCI_INT_STATUS);
sdhci_transfer_pio(host, data);
data->dest += data->blocksize;
- if (++block >= data->blocks)
- break;
+ if (++block >= data->blocks) {
+ /* Keep looping until the SDHCI_INT_DATA_END is
+ * cleared, even if we finished sending all the
+ * blocks.
+ */
+ transfer_done = true;
+ continue;
+ }
}
-#ifdef CONFIG_MMC_SDMA
- if (stat & SDHCI_INT_DMA_END) {
+#ifdef CONFIG_MMC_SDHCI_SDMA
+ if (!transfer_done && (stat & SDHCI_INT_DMA_END)) {
sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
udelay(10);
else {
printf("%s: Transfer data timeout\n", __func__);
- return -1;
+ return -ETIMEDOUT;
}
} while (!(stat & SDHCI_INT_DATA_END));
return 0;
* for card ready state.
* Every time when card is busy after timeout then (last) timeout value will be
* increased twice but only if it doesn't exceed global defined maximum.
- * Each function call will use last timeout value. Max timeout can be redefined
- * in board config file.
+ * Each function call will use last timeout value.
*/
-#ifndef CONFIG_SDHCI_CMD_MAX_TIMEOUT
-#define CONFIG_SDHCI_CMD_MAX_TIMEOUT 3200
-#endif
-#define CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT 100
+#define SDHCI_CMD_MAX_TIMEOUT 3200
+#define SDHCI_CMD_DEFAULT_TIMEOUT 100
#define SDHCI_READ_STATUS_TIMEOUT 1000
+#ifdef CONFIG_DM_MMC
+static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+
+#else
static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
- struct mmc_data *data)
+ struct mmc_data *data)
{
+#endif
struct sdhci_host *host = mmc->priv;
unsigned int stat = 0;
int ret = 0;
unsigned start = get_timer(0);
/* Timeout unit - ms */
- static unsigned int cmd_timeout = CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT;
+ static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
- sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
/* We shouldn't wait for data inihibit for stop commands, even
while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
if (time >= cmd_timeout) {
printf("%s: MMC: %d busy ", __func__, mmc_dev);
- if (2 * cmd_timeout <= CONFIG_SDHCI_CMD_MAX_TIMEOUT) {
+ if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
cmd_timeout += cmd_timeout;
printf("timeout increasing to: %u ms.\n",
cmd_timeout);
} else {
puts("timeout.\n");
- return COMM_ERR;
+ return -ECOMM;
}
}
time++;
udelay(1000);
}
+ sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
+
mask = SDHCI_INT_RESPONSE;
if (!(cmd->resp_type & MMC_RSP_PRESENT))
flags = SDHCI_CMD_RESP_NONE;
flags = SDHCI_CMD_RESP_LONG;
else if (cmd->resp_type & MMC_RSP_BUSY) {
flags = SDHCI_CMD_RESP_SHORT_BUSY;
- mask |= SDHCI_INT_DATA_END;
+ if (data)
+ mask |= SDHCI_INT_DATA_END;
} else
flags = SDHCI_CMD_RESP_SHORT;
flags |= SDHCI_CMD_DATA;
/* Set Transfer mode regarding to data flag */
- if (data != 0) {
+ if (data) {
sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
mode = SDHCI_TRNS_BLK_CNT_EN;
trans_bytes = data->blocks * data->blocksize;
if (data->flags == MMC_DATA_READ)
mode |= SDHCI_TRNS_READ;
-#ifdef CONFIG_MMC_SDMA
+#ifdef CONFIG_MMC_SDHCI_SDMA
if (data->flags == MMC_DATA_READ)
start_addr = (unsigned long)data->dest;
else
}
sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
-#ifdef CONFIG_MMC_SDMA
- flush_cache(start_addr, trans_bytes);
+#ifdef CONFIG_MMC_SDHCI_SDMA
+ if (data) {
+ trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE);
+ flush_cache(start_addr, trans_bytes);
+ }
#endif
sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
start = get_timer(0);
stat = sdhci_readl(host, SDHCI_INT_STATUS);
if (stat & SDHCI_INT_ERROR)
break;
- } while (((stat & mask) != mask) &&
- (get_timer(start) < SDHCI_READ_STATUS_TIMEOUT));
- if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
- if (host->quirks & SDHCI_QUIRK_BROKEN_R1B)
- return 0;
- else {
- printf("%s: Timeout for status update!\n", __func__);
- return TIMEOUT;
+ if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
+ if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
+ return 0;
+ } else {
+ printf("%s: Timeout for status update!\n",
+ __func__);
+ return -ETIMEDOUT;
+ }
}
- }
+ } while ((stat & mask) != mask);
if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
sdhci_cmd_done(host, cmd);
sdhci_reset(host, SDHCI_RESET_CMD);
sdhci_reset(host, SDHCI_RESET_DATA);
if (stat & SDHCI_INT_TIMEOUT)
- return TIMEOUT;
+ return -ETIMEDOUT;
else
- return COMM_ERR;
+ return -ECOMM;
}
static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
{
struct sdhci_host *host = mmc->priv;
- unsigned int div, clk, timeout, reg;
+ unsigned int div, clk = 0, timeout;
/* Wait max 20 ms */
timeout = 200;
if (timeout == 0) {
printf("%s: Timeout to wait cmd & data inhibit\n",
__func__);
- return -1;
+ return -EBUSY;
}
timeout--;
udelay(100);
}
- reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
- reg &= ~SDHCI_CLOCK_CARD_EN;
- sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
+ sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
if (clock == 0)
return 0;
if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
- /* Version 3.00 divisors must be a multiple of 2. */
- if (mmc->cfg->f_max <= clock)
- div = 1;
- else {
- for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
- if ((mmc->cfg->f_max / div) <= clock)
+ /*
+ * Check if the Host Controller supports Programmable Clock
+ * Mode.
+ */
+ if (host->clk_mul) {
+ for (div = 1; div <= 1024; div++) {
+ if ((host->max_clk / div) <= clock)
break;
}
+
+ /*
+ * Set Programmable Clock Mode in the Clock
+ * Control register.
+ */
+ clk = SDHCI_PROG_CLOCK_MODE;
+ div--;
+ } else {
+ /* Version 3.00 divisors must be a multiple of 2. */
+ if (host->max_clk <= clock) {
+ div = 1;
+ } else {
+ for (div = 2;
+ div < SDHCI_MAX_DIV_SPEC_300;
+ div += 2) {
+ if ((host->max_clk / div) <= clock)
+ break;
+ }
+ }
+ div >>= 1;
}
} else {
/* Version 2.00 divisors must be a power of 2. */
for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
- if ((mmc->cfg->f_max / div) <= clock)
+ if ((host->max_clk / div) <= clock)
break;
}
+ div >>= 1;
}
- div >>= 1;
- if (host->set_clock)
- host->set_clock(host->index, div);
+ if (host->ops && host->ops->set_clock)
+ host->ops->set_clock(host, div);
- clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
+ clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
<< SDHCI_DIVIDER_HI_SHIFT;
clk |= SDHCI_CLOCK_INT_EN;
if (timeout == 0) {
printf("%s: Internal clock never stabilised.\n",
__func__);
- return -1;
+ return -EBUSY;
}
timeout--;
udelay(1000);
return;
}
- if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
- sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
-
pwr |= SDHCI_POWER_ON;
sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
}
-static void sdhci_set_ios(struct mmc *mmc)
+#ifdef CONFIG_DM_MMC
+static int sdhci_set_ios(struct udevice *dev)
{
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+#else
+static int sdhci_set_ios(struct mmc *mmc)
+{
+#endif
u32 ctrl;
struct sdhci_host *host = mmc->priv;
- if (host->set_control_reg)
- host->set_control_reg(host);
+ if (host->ops && host->ops->set_control_reg)
+ host->ops->set_control_reg(host);
if (mmc->clock != host->clock)
sdhci_set_clock(mmc, mmc->clock);
ctrl &= ~SDHCI_CTRL_HISPD;
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+
+ /* If available, call the driver specific "post" set_ios() function */
+ if (host->ops && host->ops->set_ios_post)
+ host->ops->set_ios_post(host);
+
+ return 0;
}
static int sdhci_init(struct mmc *mmc)
{
struct sdhci_host *host = mmc->priv;
+ sdhci_reset(host, SDHCI_RESET_ALL);
+
if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
aligned_buffer = memalign(8, 512*1024);
if (!aligned_buffer) {
printf("%s: Aligned buffer alloc failed!!!\n",
__func__);
- return -1;
+ return -ENOMEM;
}
}
sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
- if (host->quirks & SDHCI_QUIRK_NO_CD) {
-#if defined(CONFIG_PIC32_SDHCI)
- /* PIC32 SDHCI CD errata:
- * - set CD_TEST and clear CD_TEST_INS bit
- */
- sdhci_writeb(host, SDHCI_CTRL_CD_TEST, SDHCI_HOST_CONTROL);
-#else
- unsigned int status;
-
- sdhci_writeb(host, SDHCI_CTRL_CD_TEST_INS | SDHCI_CTRL_CD_TEST,
- SDHCI_HOST_CONTROL);
-
- status = sdhci_readl(host, SDHCI_PRESENT_STATE);
- while ((!(status & SDHCI_CARD_PRESENT)) ||
- (!(status & SDHCI_CARD_STATE_STABLE)) ||
- (!(status & SDHCI_CARD_DETECT_PIN_LEVEL)))
- status = sdhci_readl(host, SDHCI_PRESENT_STATE);
-#endif
- }
+ if (host->ops && host->ops->get_cd)
+ host->ops->get_cd(host);
/* Enable only interrupts served by the SD controller */
sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
return 0;
}
+#ifdef CONFIG_DM_MMC
+int sdhci_probe(struct udevice *dev)
+{
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+
+ return sdhci_init(mmc);
+}
+const struct dm_mmc_ops sdhci_ops = {
+ .send_cmd = sdhci_send_command,
+ .set_ios = sdhci_set_ios,
+};
+#else
static const struct mmc_ops sdhci_ops = {
.send_cmd = sdhci_send_command,
.set_ios = sdhci_set_ios,
.init = sdhci_init,
};
+#endif
-int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
+int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
+ u32 f_max, u32 f_min)
{
- unsigned int caps;
-
- host->cfg.name = host->name;
- host->cfg.ops = &sdhci_ops;
+ u32 caps, caps_1;
caps = sdhci_readl(host, SDHCI_CAPABILITIES);
-#ifdef CONFIG_MMC_SDMA
+
+#ifdef CONFIG_MMC_SDHCI_SDMA
if (!(caps & SDHCI_CAN_DO_SDMA)) {
printf("%s: Your controller doesn't support SDMA!!\n",
__func__);
- return -1;
+ return -EINVAL;
}
#endif
+ if (host->quirks & SDHCI_QUIRK_REG32_RW)
+ host->version =
+ sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
+ else
+ host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
+
+ cfg->name = host->name;
+#ifndef CONFIG_DM_MMC
+ cfg->ops = &sdhci_ops;
+#endif
- if (max_clk)
- host->cfg.f_max = max_clk;
- else {
+ /* Check whether the clock multiplier is supported or not */
+ if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
+ caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
+ host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
+ SDHCI_CLOCK_MUL_SHIFT;
+ }
+
+ if (host->max_clk == 0) {
if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
- host->cfg.f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK)
- >> SDHCI_CLOCK_BASE_SHIFT;
+ host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
+ SDHCI_CLOCK_BASE_SHIFT;
else
- host->cfg.f_max = (caps & SDHCI_CLOCK_BASE_MASK)
- >> SDHCI_CLOCK_BASE_SHIFT;
- host->cfg.f_max *= 1000000;
+ host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
+ SDHCI_CLOCK_BASE_SHIFT;
+ host->max_clk *= 1000000;
+ if (host->clk_mul)
+ host->max_clk *= host->clk_mul;
}
- if (host->cfg.f_max == 0) {
+ if (host->max_clk == 0) {
printf("%s: Hardware doesn't specify base clock frequency\n",
__func__);
- return -1;
+ return -EINVAL;
}
- if (min_clk)
- host->cfg.f_min = min_clk;
+ if (f_max && (f_max < host->max_clk))
+ cfg->f_max = f_max;
+ else
+ cfg->f_max = host->max_clk;
+ if (f_min)
+ cfg->f_min = f_min;
else {
if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
- host->cfg.f_min = host->cfg.f_max /
- SDHCI_MAX_DIV_SPEC_300;
+ cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
else
- host->cfg.f_min = host->cfg.f_max /
- SDHCI_MAX_DIV_SPEC_200;
+ cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
}
-
- host->cfg.voltages = 0;
+ cfg->voltages = 0;
if (caps & SDHCI_CAN_VDD_330)
- host->cfg.voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
+ cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
if (caps & SDHCI_CAN_VDD_300)
- host->cfg.voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
+ cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
if (caps & SDHCI_CAN_VDD_180)
- host->cfg.voltages |= MMC_VDD_165_195;
+ cfg->voltages |= MMC_VDD_165_195;
if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
- host->cfg.voltages |= host->voltages;
+ cfg->voltages |= host->voltages;
+
+ cfg->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
- host->cfg.host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
+ /* Since Host Controller Version3.0 */
if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
- if (caps & SDHCI_CAN_DO_8BIT)
- host->cfg.host_caps |= MMC_MODE_8BIT;
+ if (!(caps & SDHCI_CAN_DO_8BIT))
+ cfg->host_caps &= ~MMC_MODE_8BIT;
}
- if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
- host->cfg.host_caps &= ~(MMC_MODE_HS | MMC_MODE_HS_52MHz);
-
if (host->host_caps)
- host->cfg.host_caps |= host->host_caps;
+ cfg->host_caps |= host->host_caps;
- host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+ cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
- sdhci_reset(host, SDHCI_RESET_ALL);
+ return 0;
+}
+
+#ifdef CONFIG_BLK
+int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
+{
+ return mmc_bind(dev, mmc, cfg);
+}
+#else
+int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
+{
+ int ret;
+
+ ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
+ if (ret)
+ return ret;
host->mmc = mmc_create(&host->cfg, host);
if (host->mmc == NULL) {
printf("%s: mmc create fail!\n", __func__);
- return -1;
+ return -ENOMEM;
}
return 0;
}
+#endif
projects / people / ms / u-boot.git / blobdiff