mmc: fix bug in mmc_startup_v4()

[people/ms/u-boot.git] / drivers / mmc / zynq_sdhci.c

diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 7887f11c649b01ae7a4565c3297f68c5f068ab18..0fddb420dc0f55745d374ca8ae39d9c7b64907ee 100644 (file)
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -1,63 +1,114 @@
 /*
- * (C) Copyright 2013 Inc.
+ * (C) Copyright 2013 - 2015 Xilinx, Inc.
  *
  * Xilinx Zynq SD Host Controller Interface
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
 
+#include <clk.h>
 #include <common.h>
+#include <dm.h>
 #include <fdtdec.h>
 #include <libfdt.h>
 #include <malloc.h>
 #include <sdhci.h>
-#include <asm/arch/sys_proto.h>
 
-int zynq_sdhci_init(phys_addr_t regbase)
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_ZYNQ_SDHCI_MIN_FREQ
+# define CONFIG_ZYNQ_SDHCI_MIN_FREQ    0
+#endif
+
+struct arasan_sdhci_plat {
+       struct mmc_config cfg;
+       struct mmc mmc;
+       unsigned int f_max;
+};
+
+static int arasan_sdhci_probe(struct udevice *dev)
 {
-       struct sdhci_host *host = NULL;
+       struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
+       struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+       struct sdhci_host *host = dev_get_priv(dev);
+       struct clk clk;
+       unsigned long clock;
+       int ret;
+
+       ret = clk_get_by_index(dev, 0, &clk);
+       if (ret < 0) {
+               dev_err(dev, "failed to get clock\n");
+               return ret;
+       }
 
-       host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
-       if (!host) {
-               printf("zynq_sdhci_init: sdhci_host malloc fail\n");
-               return 1;
+       clock = clk_get_rate(&clk);
+       if (IS_ERR_VALUE(clock)) {
+               dev_err(dev, "failed to get rate\n");
+               return clock;
        }
+       debug("%s: CLK %ld\n", __func__, clock);
 
-       host->name = "zynq_sdhci";
-       host->ioaddr = (void *)regbase;
-       host->quirks = SDHCI_QUIRK_NO_CD | SDHCI_QUIRK_WAIT_SEND_CMD |
+       ret = clk_enable(&clk);
+       if (ret && ret != -ENOSYS) {
+               dev_err(dev, "failed to enable clock\n");
+               return ret;
+       }
+
+       host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
                       SDHCI_QUIRK_BROKEN_R1B;
-       host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
 
-       host->host_caps = MMC_MODE_HC;
+#ifdef CONFIG_ZYNQ_HISPD_BROKEN
+       host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
+#endif
+
+       host->max_clk = clock;
+
+       ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max,
+                             CONFIG_ZYNQ_SDHCI_MIN_FREQ);
+       host->mmc = &plat->mmc;
+       if (ret)
+               return ret;
+       host->mmc->priv = host;
+       host->mmc->dev = dev;
+       upriv->mmc = host->mmc;
+
+       return sdhci_probe(dev);
+}
+
+static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
+{
+       struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
+       struct sdhci_host *host = dev_get_priv(dev);
+
+       host->name = dev->name;
+       host->ioaddr = (void *)devfdt_get_addr(dev);
+
+       plat->f_max = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+                               "max-frequency", CONFIG_ZYNQ_SDHCI_MAX_FREQ);
 
-       add_sdhci(host, 52000000, 52000000 >> 9);
        return 0;
 }
 
-#ifdef CONFIG_OF_CONTROL
-int zynq_sdhci_of_init(const void *blob)
+static int arasan_sdhci_bind(struct udevice *dev)
 {
-       int offset = 0;
-       u32 ret = 0;
-       phys_addr_t reg;
-
-       debug("ZYNQ SDHCI: Initialization\n");
-
-       do {
-               offset = fdt_node_offset_by_compatible(blob, offset,
-                                       "arasan,sdhci-8.9a");
-               if (offset != -1) {
-                       reg = fdtdec_get_addr(blob, offset, "reg");
-                       if (reg != FDT_ADDR_T_NONE) {
-                               ret |= zynq_sdhci_init(reg);
-                       } else {
-                               debug("ZYNQ SDHCI: Can't get base address\n");
-                               return -1;
-                       }
-               }
-       } while (offset != -1);
-
-       return ret;
+       struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
+
+       return sdhci_bind(dev, &plat->mmc, &plat->cfg);
 }
-#endif
+
+static const struct udevice_id arasan_sdhci_ids[] = {
+       { .compatible = "arasan,sdhci-8.9a" },
+       { }
+};
+
+U_BOOT_DRIVER(arasan_sdhci_drv) = {
+       .name           = "arasan_sdhci",
+       .id             = UCLASS_MMC,
+       .of_match       = arasan_sdhci_ids,
+       .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
+       .ops            = &sdhci_ops,
+       .bind           = arasan_sdhci_bind,
+       .probe          = arasan_sdhci_probe,
+       .priv_auto_alloc_size = sizeof(struct sdhci_host),
+       .platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat),
+};