Davinci: Configurable NAND chip selects

[people/ms/u-boot.git] / drivers / mtd / nand / davinci_nand.c

diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index eabaf3e773f63d8e14d46694e1a57fd394437428..1ad802a61deb4cf261a90ba39908dddcf5bde9cb 100644 (file)
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -82,26 +82,20 @@ static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int c
 
 static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
 {
-       int             dummy;
+       u_int32_t       val;
 
-       dummy = emif_regs->NANDF1ECC;
+       (void)readl(&(emif_regs->NANDFECC[CONFIG_SYS_NAND_CS - 2]));
 
-       /* FIXME:  only chipselect 0 is supported for now */
-       emif_regs->NANDFCR |= 1 << 8;
+       val = readl(&emif_regs->NANDFCR);
+       val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
+       writel(val, &emif_regs->NANDFCR);
 }
 
 static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
 {
        u_int32_t       ecc = 0;
 
-       if (region == 1)
-               ecc = emif_regs->NANDF1ECC;
-       else if (region == 2)
-               ecc = emif_regs->NANDF2ECC;
-       else if (region == 3)
-               ecc = emif_regs->NANDF3ECC;
-       else if (region == 4)
-               ecc = emif_regs->NANDF4ECC;
+       ecc = readl(&(emif_regs->NANDFECC[region - 1]));
 
        return(ecc);
 }
@@ -182,13 +176,7 @@ static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *
 
 #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
 static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = {
-/*
- * TI uses a different layout for 4K page deviecs. Since the
- * eccpos filed can hold only a limited number of entries, adding
- * support for 4K page will result in compilation warnings
- * 4K Support will be added later
- */
-#ifdef CONFIG_SYS_NAND_PAGE_2K
+#if defined(CONFIG_SYS_NAND_PAGE_2K)
        .eccbytes = 40,
        .eccpos = {
                24, 25, 26, 27, 28,
@@ -200,6 +188,21 @@ static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = {
        .oobfree = {
                {.offset = 2, .length = 22, },
        },
+#elif defined(CONFIG_SYS_NAND_PAGE_4K)
+       .eccbytes = 80,
+       .eccpos = {
+               48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
+               58, 59, 60, 61, 62, 63, 64, 65, 66, 67,
+               68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
+               78, 79, 80, 81, 82, 83, 84, 85, 86, 87,
+               88, 89, 90, 91, 92, 93, 94, 95, 96, 97,
+               98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
+               108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
+               118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
+               },
+       .oobfree = {
+               {.offset = 2, .length = 46, },
+       },
 #endif
 };
 
@@ -214,8 +217,11 @@ static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
                 * Start a new ECC calculation for reading or writing 512 bytes
                 * of data.
                 */
-               val = (emif_regs->NANDFCR & ~(3 << 4)) | (1 << 12);
-               emif_regs->NANDFCR = val;
+               val = readl(&emif_regs->NANDFCR);
+               val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
+               val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS);
+               val |= DAVINCI_NANDFCR_4BIT_ECC_START;
+               writel(val, &emif_regs->NANDFCR);
                break;
        case NAND_ECC_READSYN:
                val = emif_regs->NAND4BITECC1;