amd-xgbe: Add PCI device support

[thirdparty/kernel/stable.git] / drivers / net / ethernet / amd / xgbe / xgbe.h

diff --git a/drivers/net/ethernet/amd/xgbe/xgbe.h b/drivers/net/ethernet/amd/xgbe/xgbe.h
index 7cbf91b4aa7942443b2ce566a0226c683866529a..e22156e6088b746c946e52d00c3c8fae3e96ea76 100644 (file)
--- a/drivers/net/ethernet/amd/xgbe/xgbe.h
+++ b/drivers/net/ethernet/amd/xgbe/xgbe.h
@@ -159,7 +159,7 @@
 #define XGBE_MAX_DMA_CHANNELS  16
 #define XGBE_MAX_QUEUES                16
 #define XGBE_PRIORITY_QUEUES   8
-#define XGBE_DMA_STOP_TIMEOUT  5
+#define XGBE_DMA_STOP_TIMEOUT  1
 
 /* DMA cache settings - Outer sharable, write-back, write-allocate */
 #define XGBE_DMA_OS_AXDOMAIN   0x2
@@ -200,6 +200,20 @@
 #define XGBE_ACPI_DMA_FREQ     "amd,dma-freq"
 #define XGBE_ACPI_PTP_FREQ     "amd,ptp-freq"
 
+/* PCI BAR mapping */
+#define XGBE_XGMAC_BAR         0
+#define XGBE_XPCS_BAR          1
+#define XGBE_MAC_PROP_OFFSET   0x1d000
+#define XGBE_I2C_CTRL_OFFSET   0x1e000
+
+/* PCI MSIx support */
+#define XGBE_MSIX_BASE_COUNT   4
+#define XGBE_MSIX_MIN_COUNT    (XGBE_MSIX_BASE_COUNT + 1)
+
+/* PCI clock frequencies */
+#define XGBE_V2_DMA_CLOCK_FREQ 500000000       /* 500 MHz */
+#define XGBE_V2_PTP_CLOCK_FREQ 125000000       /* 125 MHz */
+
 /* Timestamp support - values based on 50MHz PTP clock
  *   50MHz => 20 nsec
  */
@@ -210,8 +224,6 @@
 #define XGMAC_DRIVER_CONTEXT   1
 #define XGMAC_IOCTL_CONTEXT    2
 
-#define XGMAC_FIFO_RX_MAX      81920
-#define XGMAC_FIFO_TX_MAX      81920
 #define XGMAC_FIFO_MIN_ALLOC   2048
 #define XGMAC_FIFO_UNIT                256
 #define XGMAC_FIFO_ALIGN(_x)                           \
@@ -740,6 +752,9 @@ struct xgbe_phy_if {
        /* For PHY settings validation */
        bool (*phy_valid_speed)(struct xgbe_prv_data *, int);
 
+       /* For single interrupt support */
+       irqreturn_t (*an_isr)(int, struct xgbe_prv_data *);
+
        /* PHY implementation specific services */
        struct xgbe_phy_impl_if phy_impl;
 };
@@ -805,14 +820,18 @@ struct xgbe_version_data {
        void (*init_function_ptrs_phy_impl)(struct xgbe_phy_if *);
        enum xgbe_xpcs_access xpcs_access;
        unsigned int mmc_64bit;
+       unsigned int tx_max_fifo_size;
+       unsigned int rx_max_fifo_size;
+       unsigned int tx_tstamp_workaround;
 };
 
 struct xgbe_prv_data {
        struct net_device *netdev;
-       struct platform_device *pdev;
+       struct pci_dev *pcidev;
+       struct platform_device *platdev;
        struct acpi_device *adev;
        struct device *dev;
-       struct platform_device *phy_pdev;
+       struct platform_device *phy_platdev;
        struct device *phy_dev;
 
        /* Version related data */
@@ -827,6 +846,8 @@ struct xgbe_prv_data {
        void __iomem *rxtx_regs;        /* SerDes Rx/Tx CSRs */
        void __iomem *sir0_regs;        /* SerDes integration registers (1/2) */
        void __iomem *sir1_regs;        /* SerDes integration registers (2/2) */
+       void __iomem *xprop_regs;       /* XGBE property registers */
+       void __iomem *xi2c_regs;        /* XGBE I2C CSRs */
 
        /* Overall device lock */
        spinlock_t lock;
@@ -843,8 +864,16 @@ struct xgbe_prv_data {
        /* Flags representing xgbe_state */
        unsigned long dev_state;
 
+       struct msix_entry *msix_entries;
        int dev_irq;
+       int ecc_irq;
+       int i2c_irq;
+       int channel_irq[XGBE_MAX_DMA_CHANNELS];
+
        unsigned int per_channel_irq;
+       unsigned int irq_shared;
+       unsigned int irq_count;
+       unsigned int channel_irq_count;
 
        struct xgbe_hw_if hw_if;
        struct xgbe_phy_if phy_if;
@@ -863,12 +892,16 @@ struct xgbe_prv_data {
 
        /* Rings for Tx/Rx on a DMA channel */
        struct xgbe_channel *channel;
+       unsigned int tx_max_channel_count;
+       unsigned int rx_max_channel_count;
        unsigned int channel_count;
        unsigned int tx_ring_count;
        unsigned int tx_desc_count;
        unsigned int rx_ring_count;
        unsigned int rx_desc_count;
 
+       unsigned int tx_max_q_count;
+       unsigned int rx_max_q_count;
        unsigned int tx_q_count;
        unsigned int rx_q_count;
 
@@ -880,11 +913,13 @@ struct xgbe_prv_data {
        unsigned int tx_threshold;
        unsigned int tx_pbl;
        unsigned int tx_osp_mode;
+       unsigned int tx_max_fifo_size;
 
        /* Rx settings */
        unsigned int rx_sf_mode;
        unsigned int rx_threshold;
        unsigned int rx_pbl;
+       unsigned int rx_max_fifo_size;
 
        /* Tx coalescing settings */
        unsigned int tx_usecs;
@@ -1001,14 +1036,32 @@ struct xgbe_prv_data {
 
        unsigned int debugfs_xpcs_mmd;
        unsigned int debugfs_xpcs_reg;
+
+       unsigned int debugfs_xprop_reg;
 #endif
 };
 
 /* Function prototypes*/
+struct xgbe_prv_data *xgbe_alloc_pdata(struct device *);
+void xgbe_free_pdata(struct xgbe_prv_data *);
+void xgbe_set_counts(struct xgbe_prv_data *);
+int xgbe_config_netdev(struct xgbe_prv_data *);
+void xgbe_deconfig_netdev(struct xgbe_prv_data *);
+
+int xgbe_platform_init(void);
+void xgbe_platform_exit(void);
+#ifdef CONFIG_PCI
+int xgbe_pci_init(void);
+void xgbe_pci_exit(void);
+#else
+static inline int xgbe_pci_init(void) { return 0; }
+static inline void xgbe_pci_exit(void) { }
+#endif
 
 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *);
 void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *);
 void xgbe_init_function_ptrs_phy_v1(struct xgbe_phy_if *);
+void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *);
 void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *);
 const struct net_device_ops *xgbe_get_netdev_ops(void);
 const struct ethtool_ops *xgbe_get_ethtool_ops(void);