pci/fsl_pci_init: Fold fsl_pci_setup_inbound_windows into fsl_pci_init

[people/ms/u-boot.git] / drivers / pci / fsl_pci_init.c

diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index db68f26009e22c64f04918e2dbe1ecf917a628a4..c40ab3086d02f13867b4b6c4d780a1355b3f17c3 100644 (file)
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -35,7 +35,7 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 
 #include <pci.h>
-#include <asm/immap_fsl_pci.h>
+#include <asm/fsl_pci.h>
 
 /* Freescale-specific PCI config registers */
 #define FSL_PCI_PBFR           0x44
@@ -60,7 +60,7 @@ void pciauto_config_init(struct pci_controller *hose);
 #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024)
 #endif
 
-int fsl_pci_setup_inbound_windows(struct pci_region *r)
+static int fsl_pci_setup_inbound_windows(struct pci_region *r)
 {
        struct pci_region *rgn_base = r;
        u64 sz = min((u64)gd->ram_size, (1ull << 32) - 1);
@@ -72,7 +72,7 @@ int fsl_pci_setup_inbound_windows(struct pci_region *r)
        debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
                (u64)bus_start, (u64)phys_start, (u64)pci_sz);
        pci_set_region(r++, bus_start, phys_start, pci_sz,
-                       PCI_REGION_MEM | PCI_REGION_MEMORY |
+                       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
                        PCI_REGION_PREFETCH);
 
        sz -= pci_sz;
@@ -84,7 +84,7 @@ int fsl_pci_setup_inbound_windows(struct pci_region *r)
                debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n",
                        (u64)bus_start, (u64)phys_start, (u64)pci_sz);
                pci_set_region(r++, bus_start, phys_start, pci_sz,
-                               PCI_REGION_MEM | PCI_REGION_MEMORY |
+                               PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
                                PCI_REGION_PREFETCH);
                sz -= pci_sz;
                bus_start += pci_sz;
@@ -108,7 +108,7 @@ int fsl_pci_setup_inbound_windows(struct pci_region *r)
                        CONFIG_SYS_PCI64_MEMORY_BUS,
                        CONFIG_SYS_PCI_MEMORY_PHYS,
                        pci_sz,
-                       PCI_REGION_MEM | PCI_REGION_MEMORY |
+                       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
                        PCI_REGION_PREFETCH);
 #else
        pci_sz = 1ull << __ilog2_u64(sz);
@@ -116,7 +116,7 @@ int fsl_pci_setup_inbound_windows(struct pci_region *r)
                debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n",
                        (u64)bus_start, (u64)phys_start, (u64)pci_sz);
                pci_set_region(r++, bus_start, phys_start, pci_sz,
-                               PCI_REGION_MEM | PCI_REGION_MEMORY |
+                               PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
                                PCI_REGION_PREFETCH);
                sz -= pci_sz;
                bus_start += pci_sz;
@@ -133,7 +133,7 @@ int fsl_pci_setup_inbound_windows(struct pci_region *r)
        return r - rgn_base;
 }
 
-void fsl_pci_init(struct pci_controller *hose)
+void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data)
 {
        u16 temp16;
        u32 temp32;
@@ -144,7 +144,8 @@ void fsl_pci_init(struct pci_controller *hose)
        int r;
        int bridge;
        int inbound = 0;
-       volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) hose->cfg_addr;
+       volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
+       struct pci_region *reg = hose->regions + hose->region_count;
        pci_dev_t dev = PCI_BDF(busno,0,0);
 
        /* Initialize ATMU registers based on hose regions and flags */
@@ -155,9 +156,16 @@ void fsl_pci_init(struct pci_controller *hose)
        int neg_link_w;
 #endif
 
+       pci_setup_indirect(hose, cfg_addr, cfg_data);
+
+       /* inbound */
+       reg += fsl_pci_setup_inbound_windows(reg);
+
+       hose->region_count = reg - hose->regions;
+
        for (r=0; r<hose->region_count; r++) {
                u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);
-               if (hose->regions[r].flags & PCI_REGION_MEMORY) { /* inbound */
+               if (hose->regions[r].flags & PCI_REGION_SYS_MEMORY) { /* inbound */
                        u32 flag = PIWAR_EN | PIWAR_LOCAL |
                                        PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
                        pi->pitar = (hose->regions[r].phys_start >> 12);