pci/fsl_pci_init: Fold fsl_pci_setup_inbound_windows into fsl_pci_init

[people/ms/u-boot.git] / drivers / pci / fsl_pci_init.c

diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index e57acba0d27e7ce425109410d4399d82b9514e3e..c40ab3086d02f13867b4b6c4d780a1355b3f17c3 100644 (file)
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -35,7 +35,12 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 
 #include <pci.h>
-#include <asm/immap_fsl_pci.h>
+#include <asm/fsl_pci.h>
+
+/* Freescale-specific PCI config registers */
+#define FSL_PCI_PBFR           0x44
+#define FSL_PCIE_CAP_ID                0x4c
+#define FSL_PCIE_CFG_RDY       0x4b0
 
 void pciauto_prescan_setup_bridge(struct pci_controller *hose,
                                pci_dev_t dev, int sub_bus);
@@ -55,7 +60,7 @@ void pciauto_config_init(struct pci_controller *hose);
 #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024)
 #endif
 
-int fsl_pci_setup_inbound_windows(struct pci_region *r)
+static int fsl_pci_setup_inbound_windows(struct pci_region *r)
 {
        struct pci_region *rgn_base = r;
        u64 sz = min((u64)gd->ram_size, (1ull << 32) - 1);
@@ -67,7 +72,7 @@ int fsl_pci_setup_inbound_windows(struct pci_region *r)
        debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
                (u64)bus_start, (u64)phys_start, (u64)pci_sz);
        pci_set_region(r++, bus_start, phys_start, pci_sz,
-                       PCI_REGION_MEM | PCI_REGION_MEMORY |
+                       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
                        PCI_REGION_PREFETCH);
 
        sz -= pci_sz;
@@ -79,7 +84,7 @@ int fsl_pci_setup_inbound_windows(struct pci_region *r)
                debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n",
                        (u64)bus_start, (u64)phys_start, (u64)pci_sz);
                pci_set_region(r++, bus_start, phys_start, pci_sz,
-                               PCI_REGION_MEM | PCI_REGION_MEMORY |
+                               PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
                                PCI_REGION_PREFETCH);
                sz -= pci_sz;
                bus_start += pci_sz;
@@ -103,7 +108,7 @@ int fsl_pci_setup_inbound_windows(struct pci_region *r)
                        CONFIG_SYS_PCI64_MEMORY_BUS,
                        CONFIG_SYS_PCI_MEMORY_PHYS,
                        pci_sz,
-                       PCI_REGION_MEM | PCI_REGION_MEMORY |
+                       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
                        PCI_REGION_PREFETCH);
 #else
        pci_sz = 1ull << __ilog2_u64(sz);
@@ -111,7 +116,7 @@ int fsl_pci_setup_inbound_windows(struct pci_region *r)
                debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n",
                        (u64)bus_start, (u64)phys_start, (u64)pci_sz);
                pci_set_region(r++, bus_start, phys_start, pci_sz,
-                               PCI_REGION_MEM | PCI_REGION_MEMORY |
+                               PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
                                PCI_REGION_PREFETCH);
                sz -= pci_sz;
                bus_start += pci_sz;
@@ -119,14 +124,16 @@ int fsl_pci_setup_inbound_windows(struct pci_region *r)
        }
 #endif
 
+#ifdef CONFIG_PHYS_64BIT
        if (sz && (((u64)gd->ram_size) < (1ull << 32)))
                printf("Was not able to map all of memory via "
                        "inbound windows -- %lld remaining\n", sz);
+#endif
 
        return r - rgn_base;
 }
 
-void fsl_pci_init(struct pci_controller *hose)
+void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data)
 {
        u16 temp16;
        u32 temp32;
@@ -137,7 +144,8 @@ void fsl_pci_init(struct pci_controller *hose)
        int r;
        int bridge;
        int inbound = 0;
-       volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) hose->cfg_addr;
+       volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
+       struct pci_region *reg = hose->regions + hose->region_count;
        pci_dev_t dev = PCI_BDF(busno,0,0);
 
        /* Initialize ATMU registers based on hose regions and flags */
@@ -148,9 +156,16 @@ void fsl_pci_init(struct pci_controller *hose)
        int neg_link_w;
 #endif
 
+       pci_setup_indirect(hose, cfg_addr, cfg_data);
+
+       /* inbound */
+       reg += fsl_pci_setup_inbound_windows(reg);
+
+       hose->region_count = reg - hose->regions;
+
        for (r=0; r<hose->region_count; r++) {
                u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);
-               if (hose->regions[r].flags & PCI_REGION_MEMORY) { /* inbound */
+               if (hose->regions[r].flags & PCI_REGION_SYS_MEMORY) { /* inbound */
                        u32 flag = PIWAR_EN | PIWAR_LOCAL |
                                        PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
                        pi->pitar = (hose->regions[r].phys_start >> 12);
@@ -304,6 +319,30 @@ void fsl_pci_init(struct pci_controller *hose)
        }
 }
 
+/* Enable inbound PCI config cycles for agent/endpoint interface */
+void fsl_pci_config_unlock(struct pci_controller *hose)
+{
+       pci_dev_t dev = PCI_BDF(hose->first_busno,0,0);
+       u8 agent;
+       u8 pcie_cap;
+       u16 pbfr;
+
+       pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &agent);
+       if (!agent)
+               return;
+
+       pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
+       if (pcie_cap != 0x0) {
+               /* PCIe - set CFG_READY bit of Configuration Ready Register */
+               pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1);
+       } else {
+               /* PCI - clear ACL bit of PBFR */
+               pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr);
+               pbfr &= ~0x20;
+               pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr);
+       }
+}
+
 #ifdef CONFIG_OF_BOARD_SETUP
 #include <libfdt.h>
 #include <fdt_support.h>