writel(0, ®s->pl010_cr);
break;
case TYPE_PL011:
-#ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT
- /* Empty RX fifo if necessary */
- if (readl(®s->pl011_cr) & UART_PL011_CR_UARTEN) {
- while (!(readl(®s->fr) & UART_PL01x_FR_RXFE))
- readl(®s->dr);
- }
-#endif
/* disable everything */
writel(0, ®s->pl011_cr);
break;
* control register write
*/
lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
-#ifdef CONFIG_PL011_SERIAL_RLCR
- {
- int i;
-
- /*
- * Program receive line control register after waiting
- * 10 bus cycles. Delay be writing to readonly register
- * 10 times
- */
- for (i = 0; i < 10; i++)
- writel(lcr, ®s->fr);
-
- writel(lcr, ®s->pl011_rlcr);
- }
-#endif
writel(lcr, ®s->pl011_lcrh);
return 0;
}