#include <linux/errno.h>
#include <wait_bit.h>
#include <spi.h>
+#include <malloc.h>
#include "cadence_qspi.h"
#define CQSPI_REG_POLL_US 1 /* 1us */
#define CQSPI_REG_RETRY 10000
#define CQSPI_POLL_IDLE_RETRY 3
-#define CQSPI_FIFO_WIDTH 4
-
-#define CQSPI_REG_SRAM_THRESHOLD_WORDS 50
-
/* Transfer mode */
#define CQSPI_INST_TYPE_SINGLE 0
#define CQSPI_INST_TYPE_DUAL 1
#define CQSPI_DUMMY_CLKS_PER_BYTE 8
#define CQSPI_DUMMY_BYTES_MAX 4
-#define CQSPI_REG_SRAM_FILL_THRESHOLD \
- ((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH)
-
/****************************************************************************
* Controller's configuration and status register (offset from QSPI_BASE)
****************************************************************************/
((readl(base + CQSPI_REG_CONFIG) >> \
CQSPI_REG_CONFIG_IDLE_LSB) & 0x1)
-#define CQSPI_CAL_DELAY(tdelay_ns, tref_ns, tsclk_ns) \
- ((((tdelay_ns) - (tsclk_ns)) / (tref_ns)))
-
#define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \
(((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK)
cadence_qspi_apb_controller_disable(reg_base);
/* Convert to ns. */
- ref_clk_ns = (1000000000) / ref_clk;
+ ref_clk_ns = DIV_ROUND_UP(1000000000, ref_clk);
/* Convert to ns. */
- sclk_ns = (1000000000) / sclk_hz;
-
- /* Plus 1 to round up 1 clock cycle. */
- tshsl = CQSPI_CAL_DELAY(tshsl_ns, ref_clk_ns, sclk_ns) + 1;
- tchsh = CQSPI_CAL_DELAY(tchsh_ns, ref_clk_ns, sclk_ns) + 1;
- tslch = CQSPI_CAL_DELAY(tslch_ns, ref_clk_ns, sclk_ns) + 1;
- tsd2d = CQSPI_CAL_DELAY(tsd2d_ns, ref_clk_ns, sclk_ns) + 1;
+ sclk_ns = DIV_ROUND_UP(1000000000, sclk_hz);
+
+ /* The controller adds additional delay to that programmed in the reg */
+ if (tshsl_ns >= sclk_ns + ref_clk_ns)
+ tshsl_ns -= sclk_ns + ref_clk_ns;
+ if (tchsh_ns >= sclk_ns + 3 * ref_clk_ns)
+ tchsh_ns -= sclk_ns + 3 * ref_clk_ns;
+ tshsl = DIV_ROUND_UP(tshsl_ns, ref_clk_ns);
+ tchsh = DIV_ROUND_UP(tchsh_ns, ref_clk_ns);
+ tslch = DIV_ROUND_UP(tslch_ns, ref_clk_ns);
+ tsd2d = DIV_ROUND_UP(tsd2d_ns, ref_clk_ns);
reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
<< CQSPI_REG_DELAY_TSHSL_LSB);
writel(0, plat->regbase + CQSPI_REG_REMAP);
/* Indirect mode configurations */
- writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION);
+ writel(plat->fifo_depth / 2, plat->regbase + CQSPI_REG_SRAMPARTITION);
/* Disable all interrupts */
writel(0, plat->regbase + CQSPI_REG_IRQMASK);
addr_bytes = cmdlen - 1;
/* Setup the indirect trigger address */
- writel((u32)plat->ahbbase,
+ writel(plat->trigger_address,
plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
/* Configure the opcode */
bytes_to_read = ret;
while (bytes_to_read != 0) {
- bytes_to_read *= CQSPI_FIFO_WIDTH;
+ bytes_to_read *= plat->fifo_width;
bytes_to_read = bytes_to_read > remaining ?
remaining : bytes_to_read;
- /* Handle non-4-byte aligned access to avoid data abort. */
+ /*
+ * Handle non-4-byte aligned access to avoid
+ * data abort.
+ */
if (((uintptr_t)rxbuf % 4) || (bytes_to_read % 4))
readsb(plat->ahbbase, rxbuf, bytes_to_read);
else
- readsl(plat->ahbbase, rxbuf, bytes_to_read >> 2);
+ readsl(plat->ahbbase, rxbuf,
+ bytes_to_read >> 2);
rxbuf += bytes_to_read;
remaining -= bytes_to_read;
bytes_to_read = cadence_qspi_get_rd_sram_level(plat);
}
/* Check indirect done status */
- ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_INDIRECTRD,
- CQSPI_REG_INDIRECTRD_DONE, 1, 10, 0);
+ ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTRD,
+ CQSPI_REG_INDIRECTRD_DONE, 1, 10, 0);
if (ret) {
printf("Indirect read completion error (%i)\n", ret);
goto failrd;
return -EINVAL;
}
/* Setup the indirect trigger address */
- writel((u32)plat->ahbbase,
+ writel(plat->trigger_address,
plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
/* Configure the opcode */
{
unsigned int page_size = plat->page_size;
unsigned int remaining = n_tx;
+ const u8 *bb_txbuf = txbuf;
+ void *bounce_buf = NULL;
unsigned int write_bytes;
int ret;
+ /*
+ * Use bounce buffer for non 32 bit aligned txbuf to avoid data
+ * aborts
+ */
+ if ((uintptr_t)txbuf % 4) {
+ bounce_buf = malloc(n_tx);
+ if (!bounce_buf)
+ return -ENOMEM;
+ memcpy(bounce_buf, txbuf, n_tx);
+ bb_txbuf = bounce_buf;
+ }
+
/* Configure the indirect read transfer bytes */
writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
while (remaining > 0) {
write_bytes = remaining > page_size ? page_size : remaining;
- /* Handle non-4-byte aligned access to avoid data abort. */
- if (((uintptr_t)txbuf % 4) || (write_bytes % 4))
- writesb(plat->ahbbase, txbuf, write_bytes);
- else
- writesl(plat->ahbbase, txbuf, write_bytes >> 2);
-
- ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_SDRAMLEVEL,
- CQSPI_REG_SDRAMLEVEL_WR_MASK <<
- CQSPI_REG_SDRAMLEVEL_WR_LSB, 0, 10, 0);
+ writesl(plat->ahbbase, bb_txbuf, write_bytes >> 2);
+ if (write_bytes % 4)
+ writesb(plat->ahbbase,
+ bb_txbuf + rounddown(write_bytes, 4),
+ write_bytes % 4);
+
+ ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_SDRAMLEVEL,
+ CQSPI_REG_SDRAMLEVEL_WR_MASK <<
+ CQSPI_REG_SDRAMLEVEL_WR_LSB, 0, 10, 0);
if (ret) {
printf("Indirect write timed out (%i)\n", ret);
goto failwr;
}
- txbuf += write_bytes;
+ bb_txbuf += write_bytes;
remaining -= write_bytes;
}
/* Check indirect done status */
- ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_INDIRECTWR,
- CQSPI_REG_INDIRECTWR_DONE, 1, 10, 0);
+ ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTWR,
+ CQSPI_REG_INDIRECTWR_DONE, 1, 10, 0);
if (ret) {
printf("Indirect write completion error (%i)\n", ret);
goto failwr;
/* Clear indirect completion status */
writel(CQSPI_REG_INDIRECTWR_DONE,
plat->regbase + CQSPI_REG_INDIRECTWR);
+ if (bounce_buf)
+ free(bounce_buf);
return 0;
failwr:
/* Cancel the indirect write */
writel(CQSPI_REG_INDIRECTWR_CANCEL,
plat->regbase + CQSPI_REG_INDIRECTWR);
+ if (bounce_buf)
+ free(bounce_buf);
return ret;
}
projects / people / ms / u-boot.git / blobdiff