#define TX_BUFFER_SIZE 0x40
#endif
-#define OFFSET_BITS_MASK 0x00ffffff
+#define OFFSET_BITS_MASK GENMASK(24, 0)
#define FLASH_STATUS_WEL 0x02
#define QSPI_CMD_SE_4B 0xdc /* Sector erase (usually 64KiB) */
/* fsl_qspi_platdata flags */
-#define QSPI_FLAG_REGMAP_ENDIAN_BIG (1 << 0)
+#define QSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0)
/* default SCK frequency, unit: HZ */
#define FSL_QSPI_DEFAULT_SCK_FREQ 50000000
/* Enable the module again (enable the DDR too) */
reg |= QSPI_MCR_DDR_EN_MASK;
/* Enable bit 29 for imx6sx */
- reg |= (1 << 29);
+ reg |= BIT(29);
qspi_write32(priv->flags, ®s->mcr, reg);
}