Kconfig: usb: Sort USB_FUNCTION_* entries

[people/ms/u-boot.git] / drivers / spi / zynq_qspi.c

diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
index 241a3630d39675710784ccb015b915ae5713eb3d..255e02f585da4a9a6df77d6d477b3464eafeb097 100644 (file)
--- a/drivers/spi/zynq_qspi.c
+++ b/drivers/spi/zynq_qspi.c
@@ -20,16 +20,17 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ZYNQ_QSPI_CR_MSA_MASK          BIT(15) /* Manual start enb */
 #define ZYNQ_QSPI_CR_MCS_MASK          BIT(14) /* Manual chip select */
 #define ZYNQ_QSPI_CR_PCS_MASK          BIT(10) /* Peri chip select */
-#define ZYNQ_QSPI_CR_FW_MASK           (0x3 << 6)      /* FIFO width */
-#define ZYNQ_QSPI_CR_SS_MASK           (0xF << 10)     /* Slave Select */
-#define ZYNQ_QSPI_CR_BAUD_MASK         (0x7 << 3)      /* Baud rate div */
+#define ZYNQ_QSPI_CR_FW_MASK           GENMASK(7, 6)   /* FIFO width */
+#define ZYNQ_QSPI_CR_SS_MASK           GENMASK(13, 10) /* Slave Select */
+#define ZYNQ_QSPI_CR_BAUD_MASK         GENMASK(5, 3)   /* Baud rate div */
 #define ZYNQ_QSPI_CR_CPHA_MASK         BIT(2)  /* Clock phase */
 #define ZYNQ_QSPI_CR_CPOL_MASK         BIT(1)  /* Clock polarity */
 #define ZYNQ_QSPI_CR_MSTREN_MASK       BIT(0)  /* Mode select */
 #define ZYNQ_QSPI_IXR_RXNEMPTY_MASK    BIT(4)  /* RX_FIFO_not_empty */
 #define ZYNQ_QSPI_IXR_TXOW_MASK                BIT(2)  /* TX_FIFO_not_full */
-#define ZYNQ_QSPI_IXR_ALL_MASK         0x7F            /* All IXR bits */
+#define ZYNQ_QSPI_IXR_ALL_MASK         GENMASK(6, 0)   /* All IXR bits */
 #define ZYNQ_QSPI_ENR_SPI_EN_MASK      BIT(0)  /* SPI Enable */
+#define ZYNQ_QSPI_LQSPICFG_LQMODE_MASK BIT(31) /* Linear QSPI Mode */
 
 /* zynq qspi Transmit Data Register */
 #define ZYNQ_QSPI_TXD_00_00_OFFSET     0x1C    /* Transmit 4-byte inst */
@@ -68,6 +69,9 @@ struct zynq_qspi_regs {
        u32 txd1r;      /* 0x80 */
        u32 txd2r;      /* 0x84 */
        u32 txd3r;      /* 0x88 */
+       u32 reserved1[5];
+       u32 lqspicfg;   /* 0xA0 */
+       u32 lqspists;   /* 0xA4 */
 };
 
 /* zynq qspi platform data */
@@ -97,7 +101,7 @@ static int zynq_qspi_ofdata_to_platdata(struct udevice *bus)
 {
        struct zynq_qspi_platdata *plat = bus->platdata;
        const void *blob = gd->fdt_blob;
-       int node = bus->of_offset;
+       int node = dev_of_offset(bus);
 
        plat->regs = (struct zynq_qspi_regs *)fdtdec_get_addr(blob,
                                                              node, "reg");
@@ -143,6 +147,11 @@ static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv)
                ZYNQ_QSPI_CR_MSTREN_MASK;
        writel(confr, &regs->cr);
 
+       /* Disable the LQSPI feature */
+       confr = readl(&regs->lqspicfg);
+       confr &= ~ZYNQ_QSPI_LQSPICFG_LQMODE_MASK;
+       writel(confr, &regs->lqspicfg);
+
        /* Enable SPI */
        writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
 }