#include "qemu/units.h"
#include "qemu-common.h"
#include "cpu.h"
-#include "hw/hw.h"
-#include "hw/i386/pc.h"
+#include "hw/southbridge/piix.h"
#include "hw/isa/superio.h"
-#include "hw/dma/i8257.h"
#include "hw/char/serial.h"
#include "net/net.h"
#include "hw/boards.h"
-#include "hw/i2c/smbus.h"
+#include "hw/i2c/smbus_eeprom.h"
#include "hw/block/flash.h"
#include "hw/mips/mips.h"
#include "hw/mips/cpudevs.h"
#include "qemu/log.h"
#include "hw/mips/bios.h"
#include "hw/ide.h"
+#include "hw/irq.h"
#include "hw/loader.h"
#include "elf.h"
-#include "hw/timer/mc146818rtc.h"
-#include "hw/timer/i8254.h"
#include "exec/address-spaces.h"
#include "hw/sysbus.h" /* SysBusDevice */
#include "qemu/host-utils.h"
#include "sysemu/qtest.h"
+#include "sysemu/reset.h"
+#include "sysemu/runstate.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "hw/empty_slot.h"
#include "sysemu/kvm.h"
-#include "exec/semihost.h"
+#include "hw/semihosting/semihost.h"
#include "hw/mips/cps.h"
-//#define DEBUG_BOARD_INIT
-
-#define ENVP_ADDR 0x80002000l
-#define ENVP_NB_ENTRIES 16
-#define ENVP_ENTRY_SIZE 256
+#define ENVP_ADDR 0x80002000l
+#define ENVP_NB_ENTRIES 16
+#define ENVP_ENTRY_SIZE 256
/* Hardware addresses */
-#define FLASH_ADDRESS 0x1e000000ULL
-#define FPGA_ADDRESS 0x1f000000ULL
-#define RESET_ADDRESS 0x1fc00000ULL
+#define FLASH_ADDRESS 0x1e000000ULL
+#define FPGA_ADDRESS 0x1f000000ULL
+#define RESET_ADDRESS 0x1fc00000ULL
-#define FLASH_SIZE 0x400000
+#define FLASH_SIZE 0x400000
-#define MAX_IDE_BUS 2
+#define MAX_IDE_BUS 2
typedef struct {
MemoryRegion iomem;
typedef struct {
SysBusDevice parent_obj;
- MIPSCPSState *cps;
- qemu_irq *i8259;
+ MIPSCPSState cps;
+ qemu_irq i8259[ISA_NUM_IRQS];
} MaltaState;
-static ISADevice *pit;
-
static struct _loaderparams {
int ram_size, ram_low_size;
const char *kernel_filename;
MaltaFPGAState *s = opaque;
for (i = 7 ; i >= 0 ; i--) {
- if (s->leds & (1 << i))
+ if (s->leds & (1 << i)) {
leds_text[i] = '#';
- else
+ } else {
leds_text[i] = ' ';
+ }
}
leds_text[8] = '\0';
* Typical device names include Microchip 24C02SC or SGS Thomson ST24C02.
*/
-//~ #define DEBUG
-
#if defined(DEBUG)
# define logout(fmt, ...) fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ## __VA_ARGS__)
#else
uint8_t scl;
uint8_t sda;
uint8_t data;
- //~ uint16_t size;
+ /* uint16_t size; */
uint8_t contents[256];
};
static eeprom24c0x_t spd_eeprom = {
.contents = {
- /* 00000000: */ 0x80,0x08,0xFF,0x0D,0x0A,0xFF,0x40,0x00,
- /* 00000008: */ 0x01,0x75,0x54,0x00,0x82,0x08,0x00,0x01,
- /* 00000010: */ 0x8F,0x04,0x02,0x01,0x01,0x00,0x00,0x00,
- /* 00000018: */ 0x00,0x00,0x00,0x14,0x0F,0x14,0x2D,0xFF,
- /* 00000020: */ 0x15,0x08,0x15,0x08,0x00,0x00,0x00,0x00,
- /* 00000028: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- /* 00000030: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- /* 00000038: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x12,0xD0,
- /* 00000040: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- /* 00000048: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- /* 00000050: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- /* 00000058: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- /* 00000060: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- /* 00000068: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- /* 00000070: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- /* 00000078: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x64,0xF4,
+ /* 00000000: */
+ 0x80, 0x08, 0xFF, 0x0D, 0x0A, 0xFF, 0x40, 0x00,
+ /* 00000008: */
+ 0x01, 0x75, 0x54, 0x00, 0x82, 0x08, 0x00, 0x01,
+ /* 00000010: */
+ 0x8F, 0x04, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00,
+ /* 00000018: */
+ 0x00, 0x00, 0x00, 0x14, 0x0F, 0x14, 0x2D, 0xFF,
+ /* 00000020: */
+ 0x15, 0x08, 0x15, 0x08, 0x00, 0x00, 0x00, 0x00,
+ /* 00000028: */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 00000030: */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 00000038: */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0xD0,
+ /* 00000040: */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 00000048: */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 00000050: */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 00000058: */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 00000060: */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 00000068: */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 00000070: */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ /* 00000078: */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0xF4,
},
};
/* SWITCH Register */
case 0x00200:
- val = 0x00000000; /* All switches closed */
+ /* ori a3, a3, low(ram_low_size) */
+ val = 0x00000000;
break;
/* STATUS Register */
/* GPINP Register */
case 0x00a08:
/* IN = OUT until a real I2C control is implemented */
- if (s->i2csel)
+ if (s->i2csel) {
val = s->i2cout;
- else
+ } else {
val = 0x00;
+ }
break;
/* I2CINP Register */
default:
#if 0
- printf ("malta_fpga_read: Bad register offset 0x" TARGET_FMT_lx "\n",
- addr);
+ printf("malta_fpga_read: Bad register offset 0x" TARGET_FMT_lx "\n",
+ addr);
#endif
break;
}
/* SOFTRES Register */
case 0x00500:
- if (val == 0x42)
+ if (val == 0x42) {
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+ }
break;
/* BRKRES Register */
default:
#if 0
- printf ("malta_fpga_write: Bad register offset 0x" TARGET_FMT_lx "\n",
- addr);
+ printf("malta_fpga_write: Bad register offset 0x" TARGET_FMT_lx "\n",
+ addr);
#endif
break;
}
memory_region_init_alias(&s->iomem_lo, NULL, "malta-fpga",
&s->iomem, 0, 0x900);
memory_region_init_alias(&s->iomem_hi, NULL, "malta-fpga",
- &s->iomem, 0xa00, 0x10000-0xa00);
+ &s->iomem, 0xa00, 0x10000 - 0xa00);
memory_region_add_subregion(address_space, base, &s->iomem_lo);
memory_region_add_subregion(address_space, base + 0xa00, &s->iomem_hi);
{
int i;
- for(i = 0; i < nb_nics; i++) {
+ for (i = 0; i < nb_nics; i++) {
NICInfo *nd = &nd_table[i];
const char *default_devaddr = NULL;
/* jalrc t8 */
}
-/* ROM and pseudo bootloader
-
- The following code implements a very very simple bootloader. It first
- loads the registers a0 to a3 to the values expected by the OS, and
- then jump at the kernel address.
-
- The bootloader should pass the locations of the kernel arguments and
- environment variables tables. Those tables contain the 32-bit address
- of NULL terminated strings. The environment variables table should be
- terminated by a NULL address.
-
- For a simpler implementation, the number of kernel arguments is fixed
- to two (the name of the kernel and the command line), and the two
- tables are actually the same one.
-
- The registers a0 to a3 should contain the following values:
- a0 - number of kernel arguments
- a1 - 32-bit address of the kernel arguments table
- a2 - 32-bit address of the environment variables table
- a3 - RAM size in bytes
-*/
+/*
+ * ROM and pseudo bootloader
+ *
+ * The following code implements a very very simple bootloader. It first
+ * loads the registers a0 to a3 to the values expected by the OS, and
+ * then jump at the kernel address.
+ *
+ * The bootloader should pass the locations of the kernel arguments and
+ * environment variables tables. Those tables contain the 32-bit address
+ * of NULL terminated strings. The environment variables table should be
+ * terminated by a NULL address.
+ *
+ * For a simpler implementation, the number of kernel arguments is fixed
+ * to two (the name of the kernel and the command line), and the two
+ * tables are actually the same one.
+ *
+ * The registers a0 to a3 should contain the following values:
+ * a0 - number of kernel arguments
+ * a1 - 32-bit address of the kernel arguments table
+ * a2 - 32-bit address of the environment variables table
+ * a3 - RAM size in bytes
+ */
static void write_bootloader(uint8_t *base, int64_t run_addr,
int64_t kernel_entry)
{
} else {
stl_p(p++, 0x24040002); /* addiu a0, zero, 2 */
}
- stl_p(p++, 0x3c1d0000 | (((ENVP_ADDR - 64) >> 16) & 0xffff)); /* lui sp, high(ENVP_ADDR) */
- stl_p(p++, 0x37bd0000 | ((ENVP_ADDR - 64) & 0xffff)); /* ori sp, sp, low(ENVP_ADDR) */
- stl_p(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff)); /* lui a1, high(ENVP_ADDR) */
- stl_p(p++, 0x34a50000 | (ENVP_ADDR & 0xffff)); /* ori a1, a1, low(ENVP_ADDR) */
- stl_p(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff)); /* lui a2, high(ENVP_ADDR + 8) */
- stl_p(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff)); /* ori a2, a2, low(ENVP_ADDR + 8) */
- stl_p(p++, 0x3c070000 | (loaderparams.ram_low_size >> 16)); /* lui a3, high(ram_low_size) */
- stl_p(p++, 0x34e70000 | (loaderparams.ram_low_size & 0xffff)); /* ori a3, a3, low(ram_low_size) */
+
+ /* lui sp, high(ENVP_ADDR) */
+ stl_p(p++, 0x3c1d0000 | (((ENVP_ADDR - 64) >> 16) & 0xffff));
+ /* ori sp, sp, low(ENVP_ADDR) */
+ stl_p(p++, 0x37bd0000 | ((ENVP_ADDR - 64) & 0xffff));
+ /* lui a1, high(ENVP_ADDR) */
+ stl_p(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff));
+ /* ori a1, a1, low(ENVP_ADDR) */
+ stl_p(p++, 0x34a50000 | (ENVP_ADDR & 0xffff));
+ /* lui a2, high(ENVP_ADDR + 8) */
+ stl_p(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff));
+ /* ori a2, a2, low(ENVP_ADDR + 8) */
+ stl_p(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff));
+ /* lui a3, high(ram_low_size) */
+ stl_p(p++, 0x3c070000 | (loaderparams.ram_low_size >> 16));
+ /* ori a3, a3, low(ram_low_size) */
+ stl_p(p++, 0x34e70000 | (loaderparams.ram_low_size & 0xffff));
/* Load BAR registers as done by YAMON */
stl_p(p++, 0x3c09b400); /* lui t1, 0xb400 */
}
-static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t* prom_buf, int index,
+static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t *prom_buf, int index,
const char *string, ...)
{
va_list ap;
int32_t table_addr;
- if (index >= ENVP_NB_ENTRIES)
+ if (index >= ENVP_NB_ENTRIES) {
return;
+ }
if (string == NULL) {
prom_buf[index] = 0;
}
/* Kernel */
-static int64_t load_kernel (void)
+static int64_t load_kernel(void)
{
int64_t kernel_entry, kernel_high, initrd_size;
long kernel_size;
initrd_size = 0;
initrd_offset = 0;
if (loaderparams.initrd_filename) {
- initrd_size = get_image_size (loaderparams.initrd_filename);
+ initrd_size = get_image_size(loaderparams.initrd_filename);
if (initrd_size > 0) {
- /* The kernel allocates the bootmap memory in the low memory after
- the initrd. It takes at most 128kiB for 2GB RAM and 4kiB
- pages. */
+ /*
+ * The kernel allocates the bootmap memory in the low memory after
+ * the initrd. It takes at most 128kiB for 2GB RAM and 4kiB
+ * pages.
+ */
initrd_offset = (loaderparams.ram_low_size - initrd_size
- (128 * KiB)
- ~INITRD_PAGE_MASK) & INITRD_PAGE_MASK;
prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_filename);
if (initrd_size > 0) {
- prom_set(prom_buf, prom_index++, "rd_start=0x%" PRIx64 " rd_size=%" PRId64 " %s",
- xlate_to_kseg0(NULL, initrd_offset), initrd_size,
- loaderparams.kernel_cmdline);
+ prom_set(prom_buf, prom_index++,
+ "rd_start=0x%" PRIx64 " rd_size=%" PRId64 " %s",
+ xlate_to_kseg0(NULL, initrd_offset),
+ initrd_size, loaderparams.kernel_cmdline);
} else {
prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_cmdline);
}
static void malta_mips_config(MIPSCPU *cpu)
{
+ MachineState *ms = MACHINE(qdev_get_machine());
+ unsigned int smp_cpus = ms->smp.cpus;
CPUMIPSState *env = &cpu->env;
CPUState *cs = CPU(cpu);
cpu_reset(CPU(cpu));
- /* The bootloader does not need to be rewritten as it is located in a
- read only location. The kernel location and the arguments table
- location does not change. */
+ /*
+ * The bootloader does not need to be rewritten as it is located in a
+ * read only location. The kernel location and the arguments table
+ * location does not change.
+ */
if (loaderparams.kernel_filename) {
env->CP0_Status &= ~(1 << CP0St_ERL);
}
}
}
-static void create_cpu_without_cps(const char *cpu_type,
+static void create_cpu_without_cps(MachineState *ms,
qemu_irq *cbus_irq, qemu_irq *i8259_irq)
{
CPUMIPSState *env;
MIPSCPU *cpu;
int i;
- for (i = 0; i < smp_cpus; i++) {
- cpu = MIPS_CPU(cpu_create(cpu_type));
+ for (i = 0; i < ms->smp.cpus; i++) {
+ cpu = MIPS_CPU(cpu_create(ms->cpu_type));
/* Init internal devices */
cpu_mips_irq_init_cpu(cpu);
*cbus_irq = env->irq[4];
}
-static void create_cps(MaltaState *s, const char *cpu_type,
+static void create_cps(MachineState *ms, MaltaState *s,
qemu_irq *cbus_irq, qemu_irq *i8259_irq)
{
Error *err = NULL;
- s->cps = MIPS_CPS(object_new(TYPE_MIPS_CPS));
- qdev_set_parent_bus(DEVICE(s->cps), sysbus_get_default());
-
- object_property_set_str(OBJECT(s->cps), cpu_type, "cpu-type", &err);
- object_property_set_int(OBJECT(s->cps), smp_cpus, "num-vp", &err);
- object_property_set_bool(OBJECT(s->cps), true, "realized", &err);
+ sysbus_init_child_obj(OBJECT(s), "cps", OBJECT(&s->cps), sizeof(s->cps),
+ TYPE_MIPS_CPS);
+ object_property_set_str(OBJECT(&s->cps), ms->cpu_type, "cpu-type", &err);
+ object_property_set_int(OBJECT(&s->cps), ms->smp.cpus, "num-vp", &err);
+ object_property_set_bool(OBJECT(&s->cps), true, "realized", &err);
if (err != NULL) {
error_report("%s", error_get_pretty(err));
exit(1);
}
- sysbus_mmio_map_overlap(SYS_BUS_DEVICE(s->cps), 0, 0, 1);
+ sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1);
- *i8259_irq = get_cps_irq(s->cps, 3);
+ *i8259_irq = get_cps_irq(&s->cps, 3);
*cbus_irq = NULL;
}
-static void mips_create_cpu(MaltaState *s, const char *cpu_type,
+static void mips_create_cpu(MachineState *ms, MaltaState *s,
qemu_irq *cbus_irq, qemu_irq *i8259_irq)
{
- if ((smp_cpus > 1) && cpu_supports_cps_smp(cpu_type)) {
- create_cps(s, cpu_type, cbus_irq, i8259_irq);
+ if ((ms->smp.cpus > 1) && cpu_supports_cps_smp(ms->cpu_type)) {
+ create_cps(ms, s, cbus_irq, i8259_irq);
} else {
- create_cpu_without_cps(cpu_type, cbus_irq, i8259_irq);
+ create_cpu_without_cps(ms, cbus_irq, i8259_irq);
}
}
const char *kernel_cmdline = machine->kernel_cmdline;
const char *initrd_filename = machine->initrd_filename;
char *filename;
- pflash_t *fl;
+ PFlashCFI01 *fl;
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *ram_high = g_new(MemoryRegion, 1);
MemoryRegion *ram_low_preio = g_new(MemoryRegion, 1);
MemoryRegion *ram_low_postio;
MemoryRegion *bios, *bios_copy = g_new(MemoryRegion, 1);
- target_long bios_size = FLASH_SIZE;
const size_t smbus_eeprom_size = 8 * 256;
uint8_t *smbus_eeprom_buf = g_malloc0(smbus_eeprom_size);
int64_t kernel_entry, bootloader_run_addr;
PCIBus *pci_bus;
ISABus *isa_bus;
- qemu_irq *isa_irq;
qemu_irq cbus_irq, i8259_irq;
+ PCIDevice *pci;
int piix4_devfn;
I2CBus *smbus;
DriveInfo *dinfo;
- DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
+ const size_t ide_drives = MAX_IDE_BUS * MAX_IDE_DEVS;
+ DriveInfo **hd;
int fl_idx = 0;
- int fl_sectors = bios_size >> 16;
int be;
DeviceState *dev = qdev_create(NULL, TYPE_MIPS_MALTA);
MaltaState *s = MIPS_MALTA(dev);
- /* The whole address space decoded by the GT-64120A doesn't generate
- exception when accessing invalid memory. Create an empty slot to
- emulate this feature. */
+ /*
+ * The whole address space decoded by the GT-64120A doesn't generate
+ * exception when accessing invalid memory. Create an empty slot to
+ * emulate this feature.\
+ */
empty_slot_init(0, 0x20000000);
qdev_init_nofail(dev);
/* create CPU */
- mips_create_cpu(s, machine->cpu_type, &cbus_irq, &i8259_irq);
+ mips_create_cpu(machine, s, &cbus_irq, &i8259_irq);
/* allocate RAM */
if (ram_size > 2 * GiB) {
/* Load firmware in flash / BIOS. */
dinfo = drive_get(IF_PFLASH, 0, fl_idx);
-#ifdef DEBUG_BOARD_INIT
- if (dinfo) {
- printf("Register parallel flash %d size " TARGET_FMT_lx " at "
- "addr %08llx '%s' %x\n",
- fl_idx, bios_size, FLASH_ADDRESS,
- blk_name(dinfo->bdrv), fl_sectors);
- }
-#endif
- fl = pflash_cfi01_register(FLASH_ADDRESS, NULL, "mips_malta.bios",
- BIOS_SIZE,
+ fl = pflash_cfi01_register(FLASH_ADDRESS, "mips_malta.bios",
+ FLASH_SIZE,
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
- 65536, fl_sectors,
+ 65536,
4, 0x0000, 0x0000, 0x0000, 0x0000, be);
bios = pflash_cfi01_get_memory(fl);
fl_idx++;
bootloader_run_addr, kernel_entry);
}
} else {
+ target_long bios_size = FLASH_SIZE;
/* The flash region isn't executable from a KVM guest */
if (kvm_enabled()) {
error_report("KVM enabled but no -kernel argument was specified. "
exit(1);
}
}
- /* In little endian mode the 32bit words in the bios are swapped,
- a neat trick which allows bi-endian firmware. */
+ /*
+ * In little endian mode the 32bit words in the bios are swapped,
+ * a neat trick which allows bi-endian firmware.
+ */
#ifndef TARGET_WORDS_BIGENDIAN
{
uint32_t *end, *addr;
/* Board ID = 0x420 (Malta Board with CoreLV) */
stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
- /*
- * We have a circular dependency problem: pci_bus depends on isa_irq,
- * isa_irq is provided by i8259, i8259 depends on ISA, ISA depends
- * on piix4, and piix4 depends on pci_bus. To stop the cycle we have
- * qemu_irq_proxy() adds an extra bit of indirection, allowing us
- * to resolve the isa_irq -> i8259 dependency after i8259 is initialized.
- */
- isa_irq = qemu_irq_proxy(&s->i8259, 16);
-
/* Northbridge */
- pci_bus = gt64120_register(isa_irq);
+ pci_bus = gt64120_register(s->i8259);
/* Southbridge */
- ide_drive_get(hd, ARRAY_SIZE(hd));
+ hd = g_new(DriveInfo *, ide_drives);
+ ide_drive_get(hd, ide_drives);
- piix4_devfn = piix4_init(pci_bus, &isa_bus, 80);
+ pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
+ true, TYPE_PIIX4_PCI_DEVICE);
+ dev = DEVICE(pci);
+ isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
+ piix4_devfn = pci->devfn;
/* Interrupt controller */
- /* The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 */
- s->i8259 = i8259_init(isa_bus, i8259_irq);
+ qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
+ for (int i = 0; i < ISA_NUM_IRQS; i++) {
+ s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
+ }
- isa_bus_irqs(isa_bus, s->i8259);
pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
+ g_free(hd);
pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
isa_get_irq(NULL, 9), NULL, 0, NULL);
- pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
- i8257_dma_init(isa_bus, 0);
- mc146818_rtc_init(isa_bus, 2000, NULL);
/* generate SPD EEPROM data */
generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size);
projects / thirdparty / qemu.git / blobdiff