i2c, soft-i2c: switch to new multibus/multiadapter support

[people/ms/u-boot.git] / include / configs / M5271EVB.h

diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h
index 7ddeb550b617357a797bd2825ff039b8a8a4f8ae..e8a8998fcc056693b10bbfad7d67d656d8ddac43 100644 (file)
--- a/include/configs/M5271EVB.h
+++ b/include/configs/M5271EVB.h
@@ -43,7 +43,6 @@
 #define CONFIG_MCFUART
 #define CONFIG_SYS_UART_PORT           (0)
 #define CONFIG_BAUDRATE                115200
-#define CONFIG_SYS_BAUDRATE_TABLE      { 9600 , 19200 , 38400 , 57600, 115200 }
 
 #undef CONFIG_WATCHDOG         /* disable watchdog */
 
@@ -72,6 +71,7 @@
  */
 #include <config_cmd_default.h>
 
+#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_MII
@@ -82,11 +82,12 @@
 #define CONFIG_CMD_MISC
 
 #undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMDLINE_EDITING 1 /* enables command line history */
+#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
 
 #define CONFIG_MCFFEC
 #ifdef CONFIG_MCFFEC
-#      define CONFIG_NET_MULTI         1
 #      define CONFIG_MII               1
 #      define CONFIG_MII_INIT          1
 #      define CONFIG_SYS_DISCOVER_PHY
@@ -110,13 +111,12 @@
 /* I2C */
 #define CONFIG_FSL_I2C
 #define CONFIG_HARD_I2C                /* I2C with hw support */
-#undef CONFIG_SOFT_I2C         /* I2C bit-banged */
 #define CONFIG_SYS_I2C_SPEED           80000
 #define CONFIG_SYS_I2C_SLAVE           0x7F
 #define CONFIG_SYS_I2C_OFFSET          0x00000300
 #define CONFIG_SYS_IMMR                CONFIG_SYS_MBAR
 
-#define CONFIG_BOOTDELAY       1       /* autoboot after 5 seconds */
+#define CONFIG_BOOTDELAY       1       /* autoboot after 1 seconds */
 #define CONFIG_BOOTFILE                "u-boot.bin"
 #ifdef CONFIG_MCFFEC
 #      define CONFIG_NET_RETRY_COUNT   5
@@ -128,16 +128,16 @@
 #      define CONFIG_OVERWRITE_ETHADDR_ONCE
 #endif                         /* FEC_ENET */
 
-#define CONFIG_HOSTNAME                M5235EVB
+#define CONFIG_HOSTNAME                M5271EVB
 #define CONFIG_EXTRA_ENV_SETTINGS              \
        "netdev=eth0\0"                         \
        "loadaddr=10000\0"                      \
-       "u-boot=u-boot.bin\0"                   \
-       "load=tftp ${loadaddr) ${u-boot}\0"     \
+       "uboot=u-boot.bin\0"            \
+       "load=tftp $loadaddr $uboot\0"  \
        "upd=run load; run prog\0"              \
-       "prog=prot off ffe00000 ffe2ffff;"              \
-       "era ffe00000 ffe2ffff;"                                \
-       "cp.b ${loadaddr} 0 ${filesize};"       \
+       "prog=prot off ffe00000 ffe3ffff;"      \
+       "era ffe00000 ffe3ffff;"                \
+       "cp.b $loadaddr ffe00000 $filesize;"    \
        "save\0"                                \
        ""
 
@@ -159,7 +159,17 @@
 #define CONFIG_SYS_MEMTEST_END         0x380000
 
 #define CONFIG_SYS_HZ                  1000000
+
+/* Clock configuration
+ * The external oscillator is a 25.000 MHz
+ * CONFIG_SYS_CLK for ColdFire V2 sets cpu_clk (not bus_clk)
+ * bus_clk = (cpu_clk/2) (fixed ratio)
+ *
+ * If CONFIG_SYS_CLK is changed. the CONFIG_SYS_MCF_SYNCR must be updated to
+ * match the new clock speed. Max cpu_clk is 150 MHz.
+ */
 #define CONFIG_SYS_CLK                 100000000
+#define CONFIG_SYS_MCF_SYNCR   (MCF_SYNCR_MFD_4X | MCF_SYNCR_RFD_DIV1)
 
 /*
  * Low Level Configuration Settings
@@ -173,9 +183,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR       0x20000000
-#define CONFIG_SYS_INIT_RAM_END        0x1000  /* End of used area in internal SRAM    */
-#define CONFIG_SYS_GBL_DATA_SIZE       64      /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE       0x1000  /* Size of used area in internal SRAM    */
+#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
@@ -216,7 +225,27 @@
 /* Cache Configuration */
 #define CONFIG_SYS_CACHELINE_SIZE      16
 
-/* Port configuration */
-#define CONFIG_SYS_FECI2C              0xF0
+#define ICACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
+                                        CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
+                                        CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV          (CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0          (CONFIG_SYS_SDRAM_BASE | \
+                                        CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+                                        CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR         (CF_CACR_CENB | CF_CACR_CINV | \
+                                        CF_CACR_DISD | CF_CACR_INVI | \
+                                        CF_CACR_CEIB | CF_CACR_DCM | \
+                                        CF_CACR_EUSP)
+
+/* Chip Select 0  : Boot Flash */
+#define CONFIG_SYS_CS0_BASE    0xFFE00000
+#define CONFIG_SYS_CS0_MASK    0x001F0001
+#define CONFIG_SYS_CS0_CTRL    0x00001980
+
+/* Chip Select 1 : External SRAM */
+#define CONFIG_SYS_CS1_BASE    0x30000000
+#define CONFIG_SYS_CS1_MASK    0x00070001
+#define CONFIG_SYS_CS1_CTRL    0x00001900
 
 #endif                         /* _M5271EVB_H */