drivers/mtd: Move conditional compilation to Makefile

[people/ms/u-boot.git] / include / configs / M54455EVB.h

diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
index 6f4859c238037a1e9d8d713574d92a4b82955cc2..6620f03d3d66c8d902fa47931b770638d2e9912a 100644 (file)
--- a/include/configs/M54455EVB.h
+++ b/include/configs/M54455EVB.h
@@ -27,8 +27,8 @@
  * board/config.h - configuration options, board specific
  */
 
-#ifndef _JAMICA54455_H
-#define _JAMICA54455_H
+#ifndef _M54455EVB_H
+#define _M54455EVB_H
 
 /*
  * High Level Configuration Options
@@ -38,8 +38,6 @@
 #define CONFIG_M54455          /* define processor type */
 #define CONFIG_M54455EVB       /* M54455EVB board */
 
-#undef DEBUG
-
 #define CONFIG_MCFUART
 #define CFG_UART_PORT          (0)
 #define CONFIG_BAUDRATE                115200
@@ -75,7 +73,7 @@
 #define CONFIG_CMD_MISC
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NET
-#define CONFIG_CMD_PCI
+#undef CONFIG_CMD_PCI
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 
@@ -85,9 +83,9 @@
 /* Network configuration */
 #define CONFIG_MCFFEC
 #ifdef CONFIG_MCFFEC
-#      define CONFIG_NET_MULTI 1
+#      define CONFIG_NET_MULTI         1
 #      define CONFIG_MII               1
-#      define CONFIG_CF_DOMII
+#      define CONFIG_MII_INIT          1
 #      define CFG_DISCOVER_PHY
 #      define CFG_RX_ETH_BUFFER        8
 #      define CFG_FAULT_ECHO_LINK_DOWN
@@ -129,8 +127,8 @@
        "u-boot=u-boot.bin\0"                   \
        "load=tftp ${loadaddr) ${u-boot}\0"     \
        "upd=run load; run prog\0"              \
-       "prog=prot off 0 2ffff;"                \
-       "era 0 2ffff;"                          \
+       "prog=prot off 4000000 402ffff;"                \
+       "era 4000000 402ffff;"                          \
        "cp.b ${loadaddr} 0 ${filesize};"       \
        "save\0"                                \
        ""
@@ -173,8 +171,17 @@
 #define CFG_I2C_OFFSET         0x58000
 #define CFG_IMMR               CFG_MBAR
 
+/* DSPI and Serial Flash */
+#define CONFIG_CF_DSPI
+#define CONFIG_SERIAL_FLASH
+
 /* PCI */
+#ifdef CONFIG_CMD_PCI
 #define CONFIG_PCI             1
+#define CONFIG_PCI_PNP         1
+#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE        1
+
+#define CFG_PCI_CACHE_LINE_SIZE        4
 
 #define CFG_PCI_MEM_BUS                0xA0000000
 #define CFG_PCI_MEM_PHYS       CFG_PCI_MEM_BUS
@@ -187,6 +194,7 @@
 #define CFG_PCI_CFG_BUS                0xB0000000
 #define CFG_PCI_CFG_PHYS       CFG_PCI_CFG_BUS
 #define CFG_PCI_CFG_SIZE       0x01000000
+#endif
 
 /* FPGA - Spartan 2 */
 /* experiment
@@ -268,8 +276,6 @@
 /* Configuration for environment
  * Environment is embedded in u-boot in the second sector of the flash
  */
-#define CFG_ENV_OFFSET         0x4000
-#define CFG_ENV_SECT_SIZE      0x2000
 #define CFG_ENV_IS_IN_FLASH    1
 #define CONFIG_ENV_OVERWRITE   1
 #undef CFG_ENV_IS_EMBEDDED
@@ -278,22 +284,25 @@
  * FLASH organization
  */
 #ifdef CFG_ATMEL_BOOT
-#      define CFG_FLASH_BASE           0
+#      define CFG_FLASH_BASE           CFG_CS0_BASE
 #      define CFG_FLASH0_BASE          CFG_CS0_BASE
 #      define CFG_FLASH1_BASE          CFG_CS1_BASE
+#      define CFG_ENV_ADDR             (CFG_FLASH_BASE + 0x4000)
+#      define CFG_ENV_SECT_SIZE        0x2000
 #else
-#      define CFG_FLASH_BASE           CFG_FLASH0_BASE
-#      define CFG_FLASH0_BASE          CFG_CS1_BASE
-#      define CFG_FLASH1_BASE          CFG_CS0_BASE
+#      define CFG_FLASH_BASE           CFG_CS0_BASE
+#      define CFG_FLASH0_BASE          CFG_CS0_BASE
+#      define CFG_FLASH1_BASE          CFG_CS1_BASE
+#      define CFG_ENV_ADDR             (CFG_FLASH_BASE + 0x60000)
+#      define CFG_ENV_SECT_SIZE        0x20000
 #endif
 
-/* M54455EVB has one non CFI flash, defined CFG_FLASH_CFI will cause the system
 /* M54455EVB has one non CFI flash, defined CFG_FLASH_CFI will cause the system
    keep reset. */
 #undef CFG_FLASH_CFI
 #ifdef CFG_FLASH_CFI
 
-#      define CFG_FLASH_CFI_DRIVER     1
+#      define CONFIG_FLASH_CFI_DRIVER  1
 #      define CFG_FLASH_SIZE           0x1000000       /* Max size that the board might have */
 #      define CFG_FLASH_CFI_WIDTH      FLASH_CFI_8BIT
 #      define CFG_MAX_FLASH_BANKS      2       /* max number of memory banks */
@@ -304,7 +313,7 @@
 
 #else
 
-#      define CFG_MAX_FLASH_BANKS      2       /* max number of memory banks */
+#      define CFG_MAX_FLASH_BANKS      3       /* max number of memory banks */
 
 #      define CFG_ATMEL_REGION         4
 #      define CFG_ATMEL_TOTALSECT      11
@@ -321,6 +330,28 @@
 #      define CFG_FLASH_PROTECTION     /* "Real" (hardware) sectors protection */
 #      define CFG_FLASH_CHECKSUM
 
+#ifdef CONFIG_SERIAL_FLASH
+#      define CFG_FLASH2_BASE          0x01000000
+#      define CFG_STM_SECT             32
+#      define CFG_STM_SECTSZ           0x10000
+
+#      undef CFG_FLASH_ERASE_TOUT
+#      define CFG_FLASH_ERASE_TOUT     20000
+
+#      define SER_WREN                 0x06
+#      define SER_WRDI                 0x04
+#      define SER_RDID                 0x9F
+#      define SER_RDSR                 0x05
+#      define SER_WRSR                 0x01
+#      define SER_READ                 0x03
+#      define SER_F_READ               0x0B
+#      define SER_PAGE_PROG            0x02
+#      define SER_SECT_ERASE           0xD8
+#      define SER_BULK_ERASE           0xC7
+#      define SER_DEEP_PWRDN           0xB9
+#      define SER_RES                  0xAB
+#endif
+
 #endif
 
 /*
@@ -328,9 +359,9 @@
  * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
  */
 #ifdef CFG_ATMEL_BOOT
-#      define CONFIG_JFFS2_DEV         "nor0"
+#      define CONFIG_JFFS2_DEV         "nor1"
 #      define CONFIG_JFFS2_PART_SIZE   0x01000000
-#      define CONFIG_JFFS2_PART_OFFSET CFG_FLASH1_BASE
+#      define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH1_BASE + 0x500000)
 #else
 #      define CONFIG_JFFS2_DEV         "nor0"
 #      define CONFIG_JFFS2_PART_SIZE   (0x01000000 - 0x500000)
@@ -356,20 +387,20 @@
 
 #ifdef CFG_ATMEL_BOOT
  /* Atmel Flash */
-#define CFG_CS0_BASE           0
+#define CFG_CS0_BASE           0x04000000
 #define CFG_CS0_MASK           0x00070001
 #define CFG_CS0_CTRL           0x00001140
 /* Intel Flash */
-#define CFG_CS1_BASE           0x04000000
+#define CFG_CS1_BASE           0x00000000
 #define CFG_CS1_MASK           0x01FF0001
-#define CFG_CS1_CTRL           0x003F3D60
+#define CFG_CS1_CTRL           0x00000D60
 
 #define CFG_ATMEL_BASE         CFG_CS0_BASE
 #else
 /* Intel Flash */
-#define CFG_CS0_BASE           0
+#define CFG_CS0_BASE           0x00000000
 #define CFG_CS0_MASK           0x01FF0001
-#define CFG_CS0_CTRL           0x003F3D60
+#define CFG_CS0_CTRL           0x00000D60
  /* Atmel Flash */
 #define CFG_CS1_BASE           0x04000000
 #define CFG_CS1_MASK           0x00070001
@@ -388,4 +419,4 @@
 #define CFG_CS3_MASK           0x00070001
 #define CFG_CS3_CTRL           0x00000020
 
-#endif                         /* _JAMICA54455_H */
+#endif                         /* _M54455EVB_H */