Merge git://www.denx.de/git/u-boot-marvell

[people/ms/u-boot.git] / include / configs / MPC8568MDS.h

diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index 39459ded28fc28ddb92b3dd310c2668f0539ff15..4296ba7f8bbcba2c362eed3572fe36208855a4b3 100644 (file)
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -10,20 +10,11 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_DISPLAY_BOARDINFO
-
-/* High Level Configuration Options */
-#define CONFIG_BOOKE           1       /* BOOKE */
-#define CONFIG_E500            1       /* BOOKE e500 family */
-#define CONFIG_MPC8568         1       /* MPC8568 specific */
-#define CONFIG_MPC8568MDS      1       /* MPC8568MDS board specific */
-
 #define        CONFIG_SYS_TEXT_BASE    0xfff80000
 
 #define CONFIG_SYS_SRIO
 #define CONFIG_SRIO1                   /* SRIO port 1 */
 
-#define CONFIG_PCI             1       /* Enable PCI/PCIE */
 #define CONFIG_PCI1            1       /* PCI controller */
 #define CONFIG_PCIE1           1       /* PCIE controller */
 #define CONFIG_FSL_PCI_INIT    1       /* use common fsl pci init code */
@@ -33,7 +24,6 @@
 #define CONFIG_TSEC_ENET               /* tsec ethernet support */
 #define CONFIG_QE                      /* Enable QE */
 #define CONFIG_ENV_OVERWRITE
-#define CONFIG_FSL_LAW         1       /* Use common FSL init code */
 
 #ifndef __ASSEMBLY__
 extern unsigned long get_clock_freq(void);
@@ -51,8 +41,6 @@ extern unsigned long get_clock_freq(void);
  */
 #define CONFIG_ENABLE_36BIT_PHYS       1
 
-#define CONFIG_BOARD_EARLY_INIT_F      1       /* Call board_pre_init */
-
 #define CONFIG_SYS_MEMTEST_START       0x00200000      /* memtest works on */
 #define CONFIG_SYS_MEMTEST_END         0x00400000
 
@@ -60,7 +48,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW    CONFIG_SYS_CCSRBAR
 
 /* DDR Setup */
-#define CONFIG_SYS_FSL_DDR2
 #undef CONFIG_FSL_DDR_INTERACTIVE
 #define CONFIG_SPD_EEPROM              /* Use SPD EEPROM for DDR setup*/
 #define CONFIG_DDR_SPD
@@ -71,7 +58,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_DDR_SDRAM_BASE      0x00000000      /* DDR is system memory*/
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 
-#define CONFIG_NUM_DDR_CONTROLLERS     1
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
 #define CONFIG_CHIP_SELECTS_PER_CTRL   (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 
@@ -317,9 +303,6 @@ extern unsigned long get_clock_freq(void);
 #endif /* CONFIG_QE */
 
 #if defined(CONFIG_PCI)
-
-#define CONFIG_PCI_PNP                 /* do pci plug-and-play */
-
 #undef CONFIG_EEPRO100
 #undef CONFIG_TULIP