Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx

[people/ms/u-boot.git] / include / configs / MPC8572DS.h

diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index 66e07eb302bc4f9d7fbc8605b8a960f89517c848..f98e7fbf000a2a46ed8383a84e802ec974ec9821 100644 (file)
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -42,6 +42,7 @@
 #define CONFIG_PCIE3           1       /* PCIE controler 3 (ULI bridge) */
 #define CONFIG_FSL_PCI_INIT    1       /* Use common FSL init code */
 #define CONFIG_FSL_PCIE_RESET  1       /* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT   1       /* enable 64-bit PCI resources */
 
 #define CONFIG_FSL_LAW         1       /* Use common FSL init code */
 
@@ -157,6 +158,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  * Localbus non-cacheable
  * 0xe000_0000 0xe80f_ffff     Promjet/free            128M non-cacheable
  * 0xe800_0000 0xefff_ffff     FLASH                   128M non-cacheable
+ * 0xffa0_0000 0xffaf_ffff     NAND                    1M non-cacheable
  * 0xffdf_0000 0xffdf_7fff     PIXIS                   32K non-cacheable TLB0
  * 0xffd0_0000 0xffd0_3fff     L1 for stack            16K Cacheable TLB0
  * 0xffe0_0000 0xffef_ffff     CCSR                    1M non-cacheable
@@ -259,6 +261,59 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_MONITOR_LEN         (256 * 1024) /* Reserve 256 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN          (1024 * 1024)   /* Reserved for malloc */
 
+#define CONFIG_SYS_NAND_BASE           0xffa00000
+#define CONFIG_SYS_NAND_BASE_PHYS      CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_NAND_BASE_LIST     { CONFIG_SYS_NAND_BASE,\
+                               CONFIG_SYS_NAND_BASE + 0x40000, \
+                               CONFIG_SYS_NAND_BASE + 0x80000,\
+                               CONFIG_SYS_NAND_BASE + 0xC0000}
+#define CONFIG_SYS_MAX_NAND_DEVICE    4
+#define NAND_MAX_CHIPS         1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND        1
+#define CONFIG_NAND_FSL_ELBC   1
+#define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
+
+/* NAND flash config */
+#define CONFIG_NAND_BR_PRELIM  (CONFIG_SYS_NAND_BASE_PHYS \
+                               | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+                               | BR_PS_8               /* Port Size = 8 bit */ \
+                               | BR_MS_FCM             /* MSEL = FCM */ \
+                               | BR_V)                 /* valid */
+#define CONFIG_NAND_OR_PRELIM  (0xFFFC0000            /* length 256K */ \
+                               | OR_FCM_PGS            /* Large Page*/ \
+                               | OR_FCM_CSCT \
+                               | OR_FCM_CST \
+                               | OR_FCM_CHT \
+                               | OR_FCM_SCY_1 \
+                               | OR_FCM_TRLX \
+                               | OR_FCM_EHTR)
+
+#define CONFIG_SYS_BR2_PRELIM  CONFIG_NAND_BR_PRELIM  /* NAND Base Address */
+#define CONFIG_SYS_OR2_PRELIM  CONFIG_NAND_OR_PRELIM  /* NAND Options */
+
+#define CONFIG_SYS_BR4_PRELIM  ((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)\
+                               | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+                               | BR_PS_8               /* Port Size = 8 bit */ \
+                               | BR_MS_FCM             /* MSEL = FCM */ \
+                               | BR_V)                 /* valid */
+#define CONFIG_SYS_OR4_PRELIM  CONFIG_NAND_OR_PRELIM     /* NAND Options */
+#define CONFIG_SYS_BR5_PRELIM  ((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\
+                               | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+                               | BR_PS_8               /* Port Size = 8 bit */ \
+                               | BR_MS_FCM             /* MSEL = FCM */ \
+                               | BR_V)                 /* valid */
+#define CONFIG_SYS_OR5_PRELIM  CONFIG_NAND_OR_PRELIM     /* NAND Options */
+
+#define CONFIG_SYS_BR6_PRELIM  ((CONFIG_SYS_NAND_BASE_PHYS + 0xC0000)\
+                               | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+                               | BR_PS_8               /* Port Size = 8 bit */ \
+                               | BR_MS_FCM             /* MSEL = FCM */ \
+                               | BR_V)                 /* valid */
+#define CONFIG_SYS_OR6_PRELIM  CONFIG_NAND_OR_PRELIM     /* NAND Options */
+
+
+
 /* Serial Port - controlled on board with jumper J8
  * open - index 2
  * shorted - index 1
@@ -325,11 +380,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS      0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS     0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE     0x80000000
-
 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
 #define CONFIG_SYS_PCIE3_MEM_BASE      0x80000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS      CONFIG_SYS_PCIE3_MEM_BASE
@@ -459,7 +509,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 #define CONFIG_ENV_ADDR                0xfff80000
 #else
-#define CONFIG_ENV_ADDR                (CONFIG_SYS_MONITOR_BASE + 0x70000)
+#define CONFIG_ENV_ADDR                (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
 #endif
 #define CONFIG_ENV_SIZE                0x2000
 #define CONFIG_ENV_SECT_SIZE   0x20000 /* 128K (one sector) */