arch: powerpc: update the eLBC IP input clock

[people/ms/u-boot.git] / include / configs / UCP1020.h

diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h
index 29544b28a874df333aad3c457f792a6e3548e567..a9b7a5aba9a4e0be3fc60ca06835f80aaf552ed9 100644 (file)
--- a/include/configs/UCP1020.h
+++ b/include/configs/UCP1020.h
@@ -14,7 +14,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_FSL_ELBC
 #define CONFIG_PCIE1   /* PCIE controller 1 (slot 1) */
 #define CONFIG_PCIE2   /* PCIE controller 2 (slot 2) */
 #define CONFIG_FSL_PCI_INIT    /* Use common FSL init code */
@@ -157,8 +156,6 @@
 #define CONFIG_L2_CACHE
 #define CONFIG_BTB
 
-#define CONFIG_BOARD_EARLY_INIT_F      /* Call board_pre_init */
-
 #define CONFIG_ENABLE_36BIT_PHYS
 
 #define CONFIG_SYS_MEMTEST_START       0x00200000      /* memtest works on */
@@ -176,7 +173,6 @@
 
 /* DDR Setup */
 #define CONFIG_DDR_ECC_ENABLE
-#define CONFIG_SYS_FSL_DDR3
 #ifndef CONFIG_DDR_ECC_ENABLE
 #define CONFIG_SYS_DDR_RAW_TIMING
 #define CONFIG_DDR_SPD
@@ -190,7 +186,6 @@
 #define CONFIG_SYS_DDR_SDRAM_BASE      0x00000000
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 
-#define CONFIG_NUM_DDR_CONTROLLERS     1
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
 
 /* Default settings for DDR3 */