Patch by Steven Scholz, 13 Dec 2004:

[thirdparty/u-boot.git] / include / configs / cmc_pu2.h

diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h
index e87e3184ff52420fb7254998265182e45c7d6391..a9742c19b26b2b5f3b7b1557b6227fa98907c926 100644 (file)
--- a/include/configs/cmc_pu2.h
+++ b/include/configs/cmc_pu2.h
@@ -52,6 +52,38 @@
 #define CONFIG_BOOTBINFUNC
 #endif
 
+#ifdef CONFIG_BOOTBINFUNC
+#define CFG_USE_MAIN_OSCILLATOR                1
+/* flash */
+#define MC_PUIA_VAL    0x00000000
+#define MC_PUP_VAL     0x00000000
+#define MC_PUER_VAL    0x00000000
+#define MC_ASR_VAL     0x00000000
+#define MC_AASR_VAL    0x00000000
+#define EBI_CFGR_VAL   0x00000000
+#define SMC2_CSR_VAL   0x100032ad /* 16bit, 2 TDF, 4 WS */
+
+/* clocks */
+#define PLLAR_VAL      0x202CBE04 /* 207.360 MHz for PCK */
+#define PLLBR_VAL      0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
+#define MCKR_VAL       0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */
+
+/* sdram */
+#define PIOC_ASR_VAL   0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
+#define PIOC_BSR_VAL   0x00000000
+#define PIOC_PDR_VAL   0xFFFF0000
+#define EBI_CSA_VAL    0x00000002 /* CS1=SDRAM */
+#define SDRC_CR_VAL    0x3399c1d4 /* set up the SDRAM */
+#define SDRAM          0x20000000 /* address of the SDRAM */
+#define SDRAM1         0x20000080 /* address of the SDRAM */
+#define SDRAM_VAL      0x00000000 /* value written to SDRAM */
+#define SDRC_MR_VAL    0x00000002 /* Precharge All */
+#define SDRC_MR_VAL1   0x00000004 /* refresh */
+#define SDRC_MR_VAL2   0x00000003 /* Load Mode Register */
+#define SDRC_MR_VAL3   0x00000000 /* Normal Mode */
+#define SDRC_TR_VAL    0x000002E0 /* Write refresh rate */
+#endif
+
 /*
  * Size of malloc() pool
  */