Merge git://www.denx.de/git/u-boot-marvell

[people/ms/u-boot.git] / include / configs / corenet_ds.h

diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 3807d456c7cbecd612a5fb4cbc067aa2307b5e2a..7a3de3160694dc7a873dcd2beee97a66d6cb8d8d 100644 (file)
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -24,13 +24,13 @@
 #define CONFIG_RAMBOOT_TEXT_BASE       CONFIG_SYS_TEXT_BASE
 #define CONFIG_RESET_VECTOR_ADDRESS    0xfffffffc
 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
-#if defined(CONFIG_P3041DS)
+#if defined(CONFIG_TARGET_P3041DS)
 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg
-#elif defined(CONFIG_P4080DS)
+#elif defined(CONFIG_TARGET_P4080DS)
 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg
-#elif defined(CONFIG_P5020DS)
+#elif defined(CONFIG_TARGET_P5020DS)
 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg
-#elif defined(CONFIG_P5040DS)
+#elif defined(CONFIG_TARGET_P5040DS)
 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg
 #endif
 #endif
@@ -46,9 +46,6 @@
 #endif
 
 /* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500                    /* BOOKE e500 family */
-#define CONFIG_E500MC                  /* BOOKE e500mc family */
 #define CONFIG_SYS_BOOK3E_HV           /* Category E.HV supported */
 #define CONFIG_MP                      /* support multiple processors */
 
@@ -61,7 +58,7 @@
 #endif
 
 #define CONFIG_SYS_FSL_CPC             /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC             CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_SYS_NUM_CPC             CONFIG_SYS_NUM_DDR_CTLRS
 #define CONFIG_FSL_ELBC                        /* Has Enhanced localbus controller */
 #define CONFIG_FSL_CAAM                        /* Enable SEC/CAAM */
 #define CONFIG_PCIE1                   /* PCIE controller 1 */
@@ -69,8 +66,6 @@
 #define CONFIG_FSL_PCI_INIT            /* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT           /* enable 64-bit PCI resources */
 
-#define CONFIG_FSL_LAW                 /* Use common FSL init code */
-
 #define CONFIG_ENV_OVERWRITE
 
 #ifdef CONFIG_SYS_NO_FLASH
@@ -181,7 +176,6 @@
 #define CONFIG_CHIP_SELECTS_PER_CTRL   (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 
 #define CONFIG_DDR_SPD
-#define CONFIG_SYS_FSL_DDR3
 
 #define CONFIG_SYS_SPD_BUS_NUM 1
 #define SPD_EEPROM_ADDRESS1    0x51
@@ -291,7 +285,6 @@
 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 
-#define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_EARLY_INIT_R      /* call board_early_init_r function */
 #define CONFIG_MISC_INIT_R
 
@@ -680,7 +673,7 @@
 
 #define CONFIG_BAUDRATE        115200
 
-#ifdef CONFIG_P4080DS
+#ifdef CONFIG_TARGET_P4080DS
 #define __USB_PHY_TYPE ulpi
 #else
 #define __USB_PHY_TYPE utmi