]> git.ipfire.org Git - people/ms/u-boot.git/blobdiff - include/configs/ls1012aqds.h
drivers/pci/Kconfig: Add PCI
[people/ms/u-boot.git] / include / configs / ls1012aqds.h
index 2d84095e94a6858cbe55f59b3ec5cfd04cc9319d..a8ffd6abd8bac734265ba78668fb1643f5fbde4d 100644 (file)
@@ -9,14 +9,15 @@
 
 #include "ls1012a_common.h"
 
-
+/* DDR */
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
 #define CONFIG_CHIP_SELECTS_PER_CTRL   1
 #define CONFIG_NR_DRAM_BANKS           2
 #define CONFIG_SYS_SDRAM_SIZE          0x40000000
-
-#define CONFIG_SYS_MMDC_CORE_CONTROL_1         0x05180000
-#define CONFIG_SYS_MMDC_CORE_CONTROL_2         0x85180000
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START       0x80000000
+#define CONFIG_SYS_MEMTEST_END         0x9fffffff
 
 /*
  * QIXIS Definitions
 #define CONFIG_SYS_I2C_FPGA_ADDR       0x66
 #define QIXIS_LBMAP_BRDCFG_REG         0x04
 #define QIXIS_LBMAP_SWITCH             6
-#define QIXIS_LBMAP_MASK               0xf7
+#define QIXIS_LBMAP_MASK               0x08
 #define QIXIS_LBMAP_SHIFT              0
 #define QIXIS_LBMAP_DFLTBANK           0x00
 #define QIXIS_LBMAP_ALTBANK            0x08
-#define QIXIS_RST_CTL_RESET            0x41
+#define QIXIS_RST_CTL_RESET            0x31
 #define QIXIS_RCFG_CTL_RECONFIG_IDLE   0x20
 #define QIXIS_RCFG_CTL_RECONFIG_START  0x21
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE  0x08
 #define CONFIG_HAS_FSL_XHCI_USB
 
 #ifdef CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI
 #define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_MAX_CONTROLLER_COUNT         1
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
-#define CONFIG_USB_STORAGE
 #endif
 
 /*  MMC  */
 #define CONFIG_SYS_SCSI_MAX_LUN                        1
 #define CONFIG_SYS_SCSI_MAX_DEVICE             (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
                                                CONFIG_SYS_SCSI_MAX_LUN)
-#define CONFIG_PCI             /* Enable PCI/PCIE */
 #define CONFIG_PCIE1           /* PCIE controller 1 */
 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
 #define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"