armv8: LS2080A: Rename LS2085A to reflect LS2080A

[people/ms/u-boot.git] / include / configs / ls2080a_common.h

diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2080a_common.h
similarity index 98%
rename from include/configs/ls2085a_common.h
rename to include/configs/ls2080a_common.h
index f9bca44f6f2e1004390220599b6aefe42ca8bccc..d15a2251ad096a1fd79176fa2a726b47db4d8b2d 100644 (file)
--- a/include/configs/ls2085a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -11,7 +11,7 @@
 #define CONFIG_REMAKE_ELF
 #define CONFIG_FSL_LAYERSCAPE
 #define CONFIG_FSL_LSCH3
-#define CONFIG_LS2085A
+#define CONFIG_LS2080A
 #define CONFIG_MP
 #define CONFIG_GICV3
 #define CONFIG_FSL_TZPC_BP147
@@ -20,7 +20,7 @@
 #define CONFIG_ARM_ERRATA_828024
 #define CONFIG_ARM_ERRATA_826974
 
-#include <asm/arch/ls2085a_stream_id.h>
+#include <asm/arch/ls2080a_stream_id.h>
 #include <asm/arch/config.h>
 #if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2))
 #define        CONFIG_SYS_HAS_SERDES
@@ -80,6 +80,7 @@
 #define CPU_RELEASE_ADDR               secondary_boot_func
 
 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 #define CONFIG_SYS_DP_DDR_BASE         0x6000000000ULL
 /*
  * DDR controller use 0 as the base address for binding.
@@ -88,6 +89,7 @@
 #define CONFIG_SYS_DP_DDR_BASE_PHY     0
 #define CONFIG_DP_DDR_CTRL             2
 #define CONFIG_DP_DDR_NUM_CTRLS                1
+#endif
 
 /* Generic Timer Definitions */
 /*
@@ -182,8 +184,10 @@ unsigned long long get_qixis_addr(void);
 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET    0x00F00000
 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH            0x20000
 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET    0x00F20000
+#ifndef CONFIG_LS2080A
 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH   0x200000
 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET  0x07000000
+#endif
 
 /*
  * Carve out a DDR region which will not be used by u-boot/Linux
@@ -204,7 +208,7 @@ unsigned long long get_qixis_addr(void);
 #define CONFIG_PCIE3           /* PCIE controler 3 */
 #define CONFIG_PCIE4           /* PCIE controler 4 */
 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
-#define FSL_PCIE_COMPAT "fsl,ls2085a-pcie"
+#define FSL_PCIE_COMPAT "fsl,ls2080a-pcie"
 
 #define CONFIG_SYS_PCI_64BIT