ns16550: Fix mem mapped endian check

[people/ms/u-boot.git] / include / configs / omap3_cairo.h

diff --git a/include/configs/omap3_cairo.h b/include/configs/omap3_cairo.h
index 4f8ce541448c8eb6378d9ddfc4d12fb4ebc03c76..b1f957bd5c28ffc45511eb7ca175d13a300e3387 100644 (file)
--- a/include/configs/omap3_cairo.h
+++ b/include/configs/omap3_cairo.h
@@ -29,15 +29,12 @@
  * other needs.  We use this rather than the inherited defines from
  * ti_armv7_common.h for backwards compatibility.
  */
-#define CONFIG_SYS_TEXT_BASE           0x80100000
 #define CONFIG_SYS_UBOOT_START         CONFIG_SYS_TEXT_BASE
 #define CONFIG_SPL_BSS_START_ADDR      0x80000000
 #define CONFIG_SPL_BSS_MAX_SIZE                (512 << 10)     /* 512 KB */
 #define CONFIG_SYS_SPL_MALLOC_START    0x80208000
 #define CONFIG_SYS_SPL_MALLOC_SIZE     0x100000
 
-#define CONFIG_NAND
-
 #include <configs/ti_omap3_common.h>
 
 #define CONFIG_MISC_INIT_R
@@ -51,8 +48,6 @@
 /* Probe all devices */
 #define CONFIG_SYS_I2C_NOPROBES                { {0x0, 0x0} }
 
-#define CONFIG_NAND
-
 /*
  * TWL4030
  */
@@ -61,7 +56,6 @@
 /*
  * Board NAND Info.
  */
-#define CONFIG_NAND_OMAP_GPMC
 #define CONFIG_SYS_MAX_NAND_DEVICE     1               /* Max number of NAND */
                                                        /* devices */
 #define CONFIG_EXTRA_ENV_SETTINGS \
@@ -174,16 +168,12 @@
 
 #define CONFIG_ENV_SIZE                        (128 << 10)     /* 128 KiB */
 #define ONENAND_ENV_OFFSET             0x260000 /* environment starts here */
-#define SMNAND_ENV_OFFSET              0x260000 /* environment starts here */
 
 #define CONFIG_SYS_ENV_SECT_SIZE       (128 << 10)     /* 128 KiB */
-#define CONFIG_ENV_OFFSET              SMNAND_ENV_OFFSET
-#define CONFIG_ENV_ADDR                        SMNAND_ENV_OFFSET
-
-#define CONFIG_OMAP3_SPI
+#define CONFIG_ENV_OFFSET              0x260000
+#define CONFIG_ENV_ADDR                        0x260000
 
 /* Defines for SPL */
-#define CONFIG_SPL_OMAP3_ID_NAND
 
 /* NAND boot config */
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
@@ -200,9 +190,7 @@
 #define CONFIG_SYS_NAND_U_BOOT_OFFS    0x80000
 /* NAND: SPL falcon mode configs */
 #ifdef CONFIG_SPL_OS_BOOT
-#define CONFIG_CMD_SPL_NAND_OFS                0x240000
 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS        0x280000
-#define CONFIG_CMD_SPL_WRITE_SIZE      0x2000
 #endif
 
 /* env defaults */