powerpc/85xx: Update default hwconfig on P1022DS

[people/ms/u-boot.git] / include / ddr_spd.h

diff --git a/include/ddr_spd.h b/include/ddr_spd.h
index 10402c5bbb242c4b48d6832b886fa4180edb40ee..e895d615a8d53ea12df765676e9b649213fac01e 100644 (file)
--- a/include/ddr_spd.h
+++ b/include/ddr_spd.h
@@ -243,6 +243,20 @@ typedef struct ddr3_spd_eeprom_s {
                        unsigned char mod_thickness;
                        /* 62 (Registered) Reference Raw Card Used */
                        unsigned char ref_raw_card;
+                       /* 63 DIMM Module Attributes */
+                       unsigned char modu_attr;
+                       /* 64 RDIMM Thermal Heat Spreader Solution */
+                       unsigned char thermal;
+                       /* 65 Register Manufacturer ID Code, Least Significant Byte */
+                       unsigned char reg_id_lo;
+                       /* 66 Register Manufacturer ID Code, Most Significant Byte */
+                       unsigned char reg_id_hi;
+                       /* 67 Register Revision Number */
+                       unsigned char reg_rev;
+                       /* 68 Register Type */
+                       unsigned char reg_type;
+                       /* 69-76 RC1,3,5...15 (MS Nibble) / RC0,2,4...14 (LS Nibble) */
+                       unsigned char rcw[8];
                } registered;
                unsigned char uc[57]; /* 60-116 Module-Specific Section */
        } mod_section;
@@ -290,14 +304,24 @@ extern unsigned int ddr3_spd_check(const ddr3_spd_eeprom_t *spd);
 #define SPD_MEMTYPE_DDR2_FBDIMM_PROBE  (0x0A)
 #define SPD_MEMTYPE_DDR3       (0x0B)
 
-/*
- * Byte 3 Key Byte / Module Type for DDR3 SPD
- */
-#define SPD_MODULETYPE_RDIMM           (0x01)
-#define SPD_MODULETYPE_UDIMM           (0x02)
-#define SPD_MODULETYPE_SODIMM          (0x03)
-#define SPD_MODULETYPE_MICRODIMM       (0x04)
-#define SPD_MODULETYPE_MINIRDIMM       (0x05)
-#define SPD_MODULETYPE_MINIUDIMM       (0x06)
+/* DIMM Type for DDR2 SPD (according to v1.3) */
+#define DDR2_SPD_DIMMTYPE_UNDEFINED    (0x00)
+#define DDR2_SPD_DIMMTYPE_RDIMM                (0x01)
+#define DDR2_SPD_DIMMTYPE_UDIMM                (0x02)
+#define DDR2_SPD_DIMMTYPE_SO_DIMM      (0x04)
+#define DDR2_SPD_DIMMTYPE_72B_SO_CDIMM (0x06)
+#define DDR2_SPD_DIMMTYPE_72B_SO_RDIMM (0x07)
+#define DDR2_SPD_DIMMTYPE_MICRO_DIMM   (0x08)
+#define DDR2_SPD_DIMMTYPE_MINI_RDIMM   (0x10)
+#define DDR2_SPD_DIMMTYPE_MINI_UDIMM   (0x20)
+
+/* Byte 3 Key Byte / Module Type for DDR3 SPD */
+#define DDR3_SPD_MODULETYPE_MASK       (0x0f)
+#define DDR3_SPD_MODULETYPE_RDIMM      (0x01)
+#define DDR3_SPD_MODULETYPE_UDIMM      (0x02)
+#define DDR3_SPD_MODULETYPE_SO_DIMM    (0x03)
+#define DDR3_SPD_MODULETYPE_MICRO_DIMM (0x04)
+#define DDR3_SPD_MODULETYPE_MINI_RDIMM (0x05)
+#define DDR3_SPD_MODULETYPE_MINI_UDIMM (0x06)
 
 #endif /* _DDR_SPD_H_ */