Squashed 'dts/upstream/' changes from aaba2d45dc2a..b35b9bd1d4ee

[thirdparty/u-boot.git] / include / dt-bindings / reset / mt8188-resets.h

diff --git a/include/dt-bindings/reset/mt8188-resets.h b/include/dt-bindings/reset/mt8188-resets.h
index ba9a5e9b889981d6191bc55468ce49566a515897..5a58c54e7d200cae37b8bfc205c472919368be82 100644 (file)
--- a/include/dt-bindings/reset/mt8188-resets.h
+++ b/include/dt-bindings/reset/mt8188-resets.h
@@ -38,4 +38,79 @@
 #define MT8188_INFRA_RST1_THERMAL_CTRL_RST         1
 #define MT8188_INFRA_RST3_PTP_CTRL_RST             2
 
+#define MT8188_VDO0_RST_DISP_OVL0              0
+#define MT8188_VDO0_RST_FAKE_ENG0              1
+#define MT8188_VDO0_RST_DISP_CCORR0            2
+#define MT8188_VDO0_RST_DISP_MUTEX0            3
+#define MT8188_VDO0_RST_DISP_GAMMA0            4
+#define MT8188_VDO0_RST_DISP_DITHER0           5
+#define MT8188_VDO0_RST_DISP_WDMA0             6
+#define MT8188_VDO0_RST_DISP_RDMA0             7
+#define MT8188_VDO0_RST_DSI0                   8
+#define MT8188_VDO0_RST_DSI1                   9
+#define MT8188_VDO0_RST_DSC_WRAP0              10
+#define MT8188_VDO0_RST_VPP_MERGE0             11
+#define MT8188_VDO0_RST_DP_INTF0               12
+#define MT8188_VDO0_RST_DISP_AAL0              13
+#define MT8188_VDO0_RST_INLINEROT0             14
+#define MT8188_VDO0_RST_APB_BUS                        15
+#define MT8188_VDO0_RST_DISP_COLOR0            16
+#define MT8188_VDO0_RST_MDP_WROT0              17
+#define MT8188_VDO0_RST_DISP_RSZ0              18
+
+#define MT8188_VDO1_RST_SMI_LARB2              0
+#define MT8188_VDO1_RST_SMI_LARB3              1
+#define MT8188_VDO1_RST_GALS                   2
+#define MT8188_VDO1_RST_FAKE_ENG0              3
+#define MT8188_VDO1_RST_FAKE_ENG1              4
+#define MT8188_VDO1_RST_MDP_RDMA0              5
+#define MT8188_VDO1_RST_MDP_RDMA1              6
+#define MT8188_VDO1_RST_MDP_RDMA2              7
+#define MT8188_VDO1_RST_MDP_RDMA3              8
+#define MT8188_VDO1_RST_VPP_MERGE0             9
+#define MT8188_VDO1_RST_VPP_MERGE1             10
+#define MT8188_VDO1_RST_VPP_MERGE2             11
+#define MT8188_VDO1_RST_VPP_MERGE3             12
+#define MT8188_VDO1_RST_VPP_MERGE4             13
+#define MT8188_VDO1_RST_VPP2_TO_VDO1_DL_ASYNC  14
+#define MT8188_VDO1_RST_VPP3_TO_VDO1_DL_ASYNC  15
+#define MT8188_VDO1_RST_DISP_MUTEX             16
+#define MT8188_VDO1_RST_MDP_RDMA4              17
+#define MT8188_VDO1_RST_MDP_RDMA5              18
+#define MT8188_VDO1_RST_MDP_RDMA6              19
+#define MT8188_VDO1_RST_MDP_RDMA7              20
+#define MT8188_VDO1_RST_DP_INTF1_MMCK          21
+#define MT8188_VDO1_RST_DPI0_MM_CK             22
+#define MT8188_VDO1_RST_DPI1_MM_CK             23
+#define MT8188_VDO1_RST_MERGE0_DL_ASYNC                24
+#define MT8188_VDO1_RST_MERGE1_DL_ASYNC                25
+#define MT8188_VDO1_RST_MERGE2_DL_ASYNC                26
+#define MT8188_VDO1_RST_MERGE3_DL_ASYNC                27
+#define MT8188_VDO1_RST_MERGE4_DL_ASYNC                28
+#define MT8188_VDO1_RST_VDO0_DSC_TO_VDO1_DL_ASYNC      29
+#define MT8188_VDO1_RST_VDO0_MERGE_TO_VDO1_DL_ASYNC    30
+#define MT8188_VDO1_RST_PADDING0               31
+#define MT8188_VDO1_RST_PADDING1               32
+#define MT8188_VDO1_RST_PADDING2               33
+#define MT8188_VDO1_RST_PADDING3               34
+#define MT8188_VDO1_RST_PADDING4               35
+#define MT8188_VDO1_RST_PADDING5               36
+#define MT8188_VDO1_RST_PADDING6               37
+#define MT8188_VDO1_RST_PADDING7               38
+#define MT8188_VDO1_RST_DISP_RSZ0              39
+#define MT8188_VDO1_RST_DISP_RSZ1              40
+#define MT8188_VDO1_RST_DISP_RSZ2              41
+#define MT8188_VDO1_RST_DISP_RSZ3              42
+#define MT8188_VDO1_RST_HDR_VDO_FE0            43
+#define MT8188_VDO1_RST_HDR_GFX_FE0            44
+#define MT8188_VDO1_RST_HDR_VDO_BE             45
+#define MT8188_VDO1_RST_HDR_VDO_FE1            46
+#define MT8188_VDO1_RST_HDR_GFX_FE1            47
+#define MT8188_VDO1_RST_DISP_MIXER             48
+#define MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC   49
+#define MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC   50
+#define MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC   51
+#define MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC   52
+#define MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC    53
+
 #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */