Merge branch 'master' of git://git.denx.de/u-boot-video

[people/ms/u-boot.git] / include / fsl_ddr_sdram.h

diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
index e8a2db91cb7e115275ae13c70a498de4ee518239..3699c0408a11aeeee2354b471e5a63174f12d924 100644 (file)
--- a/include/fsl_ddr_sdram.h
+++ b/include/fsl_ddr_sdram.h
@@ -1,9 +1,7 @@
 /*
  * Copyright 2008-2014 Freescale Semiconductor, Inc.
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier:    GPL-2.0
  */
 
 #ifndef FSL_DDR_MEMCTL_H
@@ -33,6 +31,15 @@
 #define DDR3_RTT_20_OHM                4 /* RTT_Nom = RZQ/12 */
 #define DDR3_RTT_30_OHM                5 /* RTT_Nom = RZQ/8 */
 
+#define DDR4_RTT_OFF           0
+#define DDR4_RTT_60_OHM                1       /* RZQ/4 */
+#define DDR4_RTT_120_OHM       2       /* RZQ/2 */
+#define DDR4_RTT_40_OHM                3       /* RZQ/6 */
+#define DDR4_RTT_240_OHM       4       /* RZQ/1 */
+#define DDR4_RTT_48_OHM                5       /* RZQ/5 */
+#define DDR4_RTT_80_OHM                6       /* RZQ/3 */
+#define DDR4_RTT_34_OHM                7       /* RZQ/7 */
+
 #define DDR2_RTT_OFF           0
 #define DDR2_RTT_75_OHM                1
 #define DDR2_RTT_150_OHM       2
@@ -51,7 +58,6 @@ typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
 #define CONFIG_FSL_SDRAM_TYPE  SDRAM_TYPE_DDR2
 #endif
 #elif defined(CONFIG_SYS_FSL_DDR3)
-#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR       (3)     /* FIXME */
 typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
 #ifndef CONFIG_FSL_SDRAM_TYPE
 #define CONFIG_FSL_SDRAM_TYPE  SDRAM_TYPE_DDR3
@@ -115,6 +121,7 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
 #define SDRAM_CFG_2T_EN                        0x00008000
 #define SDRAM_CFG_BI                   0x00000001
 
+#define SDRAM_CFG2_FRC_SR              0x80000000
 #define SDRAM_CFG2_D_INIT              0x00000010
 #define SDRAM_CFG2_ODT_CFG_MASK                0x00600000
 #define SDRAM_CFG2_ODT_NEVER           0
@@ -122,6 +129,7 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
 #define SDRAM_CFG2_ODT_ONLY_READ       2
 #define SDRAM_CFG2_ODT_ALWAYS          3
 
+#define SDRAM_INTERVAL_BSTOPRE 0x3FFF
 #define TIMING_CFG_2_CPO_MASK  0x0F800000
 
 #if defined(CONFIG_SYS_FSL_DDR_VER) && \
@@ -155,6 +163,8 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
 #define MD_CNTL_CKE_CNTL_HIGH  0x00200000
 #define MD_CNTL_WRCW           0x00080000
 #define MD_CNTL_MD_VALUE(x)    (x & 0x0000FFFF)
+#define MD_CNTL_CS_SEL(x)      (((x) & 0x7) << 28)
+#define MD_CNTL_MD_SEL(x)      (((x) & 0xf) << 24)
 
 /* DDR_CDR1 */
 #define DDR_CDR1_DHC_EN        0x80000000
@@ -164,6 +174,8 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
 #define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT)
 #define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)
 #define DDR_CDR2_VREF_OVRD(x)  (0x00008080 | ((((x) - 37) & 0x3F) << 8))
+#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
+#define DDR_CDR2_VREF_RANGE_2  0x00000040
 
 #if (defined(CONFIG_SYS_FSL_DDR_VER) && \
        (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
@@ -203,6 +215,8 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
 #define DDR_CDR_ODT_120ohm     0x6
 #endif
 
+#define DDR_INIT_ADDR_EXT_UIA  (1 << 31)
+
 /* Record of register values computed */
 typedef struct fsl_ddr_cfg_regs_s {
        struct {
@@ -281,6 +295,7 @@ typedef struct memctl_options_partial_s {
 #define DDR_DATA_BUS_WIDTH_64 0
 #define DDR_DATA_BUS_WIDTH_32 1
 #define DDR_DATA_BUS_WIDTH_16 2
+#define DDR_CSWL_CS0   0x04000001
 /*
  * Generalized parameters for memory controller configuration,
  * might be a little specific to the FSL memory controller
@@ -317,6 +332,8 @@ typedef struct memctl_options_s {
        unsigned int dqs_config;        /* Use DQS? maybe only with DDR2? */
        /* SREN - self-refresh during sleep */
        unsigned int self_refresh_in_sleep;
+       /* SR_IE - Self-refresh interrupt enable */
+       unsigned int self_refresh_interrupt_en;
        unsigned int dynamic_power;     /* DYN_PWR */
        /* memory data width to use (16-bit, 32-bit, 64-bit) */
        unsigned int data_bus_width;
@@ -340,6 +357,7 @@ typedef struct memctl_options_s {
        unsigned int cpo_override;
        unsigned int write_data_delay;          /* DQS adjust */
 
+       unsigned int cswl_override;
        unsigned int wrlvl_override;
        unsigned int wrlvl_sample;              /* Write leveling */
        unsigned int wrlvl_start;
@@ -350,7 +368,6 @@ typedef struct memctl_options_s {
        unsigned int twot_en;
        unsigned int threet_en;
        unsigned int bstopre;
-       unsigned int tcke_clock_pulse_width_ps; /* tCKE */
        unsigned int tfaw_window_four_activates_ps;     /* tFAW --  FOUR_ACT */
 
        /* Rtt impedance */
@@ -377,12 +394,20 @@ typedef struct memctl_options_s {
        unsigned int trwt;                      /* read-to-write turnaround */
 } memctl_options_t;
 
-extern phys_size_t fsl_ddr_sdram(void);
-extern phys_size_t fsl_ddr_sdram_size(void);
+phys_size_t fsl_ddr_sdram(void);
+phys_size_t fsl_ddr_sdram_size(void);
+phys_size_t fsl_other_ddr_sdram(unsigned long long base,
+                               unsigned int first_ctrl,
+                               unsigned int num_ctrls,
+                               unsigned int dimm_slots_per_ctrl,
+                               int (*board_need_reset)(void),
+                               void (*board_reset)(void),
+                               void (*board_de_reset)(void));
 extern int fsl_use_spd(void);
-extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
-                                       unsigned int ctrl_num, int step);
+void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
+                            unsigned int ctrl_num, int step);
 u32 fsl_ddr_get_intl3r(void);
+void print_ddr_info(unsigned int start_ctrl);
 
 static void __board_assert_mem_reset(void)
 {
@@ -406,9 +431,11 @@ static int __board_need_mem_reset(void)
 int board_need_mem_reset(void)
        __attribute__((weak, alias("__board_need_mem_reset")));
 
-void __weak board_mem_sleep_setup(void)
-{
-}
+#if defined(CONFIG_DEEP_SLEEP)
+void board_mem_sleep_setup(void);
+bool is_warm_boot(void);
+int fsl_dp_resume(void);
+#endif
 
 /*
  * The 85xx boards have a common prototype for fixed_sdram so put the