rename CFG_ macros to CONFIG_SYS

[people/ms/u-boot.git] / post / board / lwmon5 / fpga.c

diff --git a/post/board/lwmon5/fpga.c b/post/board/lwmon5/fpga.c
index dca7a30a98e714012c2b04ff6d34d214fc21aa2e..2b842908db2f2e037c233eabd464438539d6ad55 100644 (file)
--- a/post/board/lwmon5/fpga.c
+++ b/post/board/lwmon5/fpga.c
@@ -23,8 +23,6 @@
  */
 #include <common.h>
 
-#ifdef CONFIG_POST
-
 /* This test performs testing of FPGA SCRATCH register,
  * gets FPGA version and run get_ram_size() on FPGA memory
  */
@@ -41,17 +39,16 @@ DECLARE_GLOBAL_DATA_PTR;
 #define FPGA_RAM_END           0xC4203FFF
 #define FPGA_STAT              0xC400000C
 
-#define FPGA_PWM_CTRL_REG      0xC4000020
-#define FPGA_PWM_TV_REG                0xC4000024
-
-/* Turn on backlight, set brightness */
-void fpga_backlight_enable(int pwm)
-{
-       out_be16((void *)FPGA_PWM_CTRL_REG, 0x0701);
-       out_be16((void *)FPGA_PWM_TV_REG, pwm);
-}
+#if CONFIG_POST & CONFIG_SYS_POST_BSPEC3
 
-#if CONFIG_POST & CFG_POST_BSPEC3
+/* Testpattern for fpga memorytest */
+static uint pattern[] = {
+       0x55555555,
+       0xAAAAAAAA,
+       0xAA5555AA,
+       0x55AAAA55,
+       0x0
+};
 
 static int one_scratch_test(uint value)
 {
@@ -72,9 +69,42 @@ static int one_scratch_test(uint value)
        return ret;
 }
 
+/* FPGA Memory-pattern-test */
+static int fpga_mem_test(void * address)
+{
+       int ret = 1;
+       uint read_value;
+       uint old_value;
+       uint i = 0;
+       /* save content */
+       old_value = in_be32(address);
+
+       while (pattern[i] != 0) {
+               out_be32(address, pattern[i]);
+               /* read other location (protect against data lines capacity) */
+               ret = in_be16((void *)FPGA_VERSION_REG);
+               /* verify test pattern */
+               read_value = in_be32(address);
+
+               if (read_value != pattern[i]) {
+                       post_log("FPGA Memory test failed.");
+                       post_log(" write %08X, read %08X at address %08X\n",
+                               pattern[i], read_value, address);
+                       ret = 1;
+                       goto out;
+               }
+               i++;
+       }
+
+       ret = 0;
+out:
+       out_be32(address, old_value);
+       return ret;
+}
 /* Verify FPGA, get version & memory size */
 int fpga_post_test(int flags)
 {
+       uint   address;
        uint   old_value;
        ushort version;
        uint   read_value;
@@ -97,11 +127,18 @@ int fpga_post_test(int flags)
        /* Enable write to FPGA RAM */
        out_be32((void *)FPGA_STAT, in_be32((void *)FPGA_STAT) | 0x1000);
 
-       read_value = get_ram_size((void *)CFG_FPGA_BASE_1, 0x4000);
+       read_value = get_ram_size((void *)CONFIG_SYS_FPGA_BASE_1, 0x4000);
        post_log("FPGA RAM size: %d bytes\n", read_value);
 
+       for (address = 0; address < 0x1000; address++) {
+               if (fpga_mem_test((void *)(FPGA_RAM_START + 4*address)) == 1) {
+                       ret = 1;
+                       goto out;
+               }
+       }
+
+out:
        return ret;
 }
 
-#endif /* CONFIG_POST & CFG_POST_BSPEC3 */
-#endif /* CONFIG_POST */
+#endif /* CONFIG_POST & CONFIG_SYS_POST_BSPEC3 */