Squashed 'dts/upstream/' changes from aaba2d45dc2a..b35b9bd1d4ee

[thirdparty/u-boot.git] / src / arm64 / qcom / sc8280xp.dtsi

diff --git a/src/arm64/qcom/sc8280xp.dtsi b/src/arm64/qcom/sc8280xp.dtsi
index cad59af7ccef1b599d958f0a0f94fa800895d0bb..febf28356ff8b0a4a52de16ceda2ab1bdb1eca4d 100644 (file)
--- a/src/arm64/qcom/sc8280xp.dtsi
+++ b/src/arm64/qcom/sc8280xp.dtsi
@@ -8,6 +8,7 @@
 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
 #include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,sc8280xp-camcc.h>
 #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
 #include <dt-bindings/interconnect/qcom,osm-l3.h>
 #include <dt-bindings/interconnect/qcom,sc8280xp.h>
@@ -2731,7 +2732,7 @@
                        status = "disabled";
                };
 
-               swr1: soundwire-controller@3210000 {
+               swr1: soundwire@3210000 {
                        compatible = "qcom,soundwire-v1.6.0";
                        reg = <0 0x03210000 0 0x2000>;
                        interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
@@ -2807,7 +2808,7 @@
                        status = "disabled";
                };
 
-               swr0: soundwire-controller@3250000 {
+               swr0: soundwire@3250000 {
                        reg = <0 0x03250000 0 0x2000>;
                        compatible = "qcom,soundwire-v1.6.0";
                        interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
@@ -2844,7 +2845,7 @@
                        #reset-cells = <1>;
                };
 
-               swr2: soundwire-controller@3330000 {
+               swr2: soundwire@3330000 {
                        compatible = "qcom,soundwire-v1.6.0";
                        reg = <0 0x03330000 0 0x2000>;
                        interrupts = <GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>,
@@ -3450,6 +3451,20 @@
                        };
                };
 
+               camcc: clock-controller@ad00000 {
+                       compatible = "qcom,sc8280xp-camcc";
+                       reg = <0 0x0ad00000 0 0x20000>;
+                       clocks = <&gcc GCC_CAMERA_AHB_CLK>,
+                                <&rpmhcc RPMH_CXO_CLK>,
+                                <&rpmhcc RPMH_CXO_CLK_A>,
+                                <&sleep_clk>;
+                       power-domains = <&rpmhpd SC8280XP_MMCX>;
+                       required-opps = <&rpmhpd_opp_low_svs>;
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+                       #power-domain-cells = <1>;
+               };
+
                mdss0: display-subsystem@ae00000 {
                        compatible = "qcom,sc8280xp-mdss";
                        reg = <0 0x0ae00000 0 0x1000>;
@@ -4030,6 +4045,7 @@
                sram@c3f0000 {
                        compatible = "qcom,rpmh-stats";
                        reg = <0 0x0c3f0000 0 0x400>;
+                       qcom,qmp = <&aoss_qmp>;
                };
 
                spmi_bus: spmi@c440000 {
@@ -4225,7 +4241,7 @@
                        compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt";
                        reg = <0 0x17c10000 0 0x1000>;
                        clocks = <&sleep_clk>;
-                       interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
                };
 
                timer@17c20000 {