X-Git-Url: http://git.ipfire.org/?a=blobdiff_plain;f=arch%2Farm%2Fmach-socfpga%2FKconfig;h=e4cc468e723a963c2e7f90f53b0d0f6a967bc1cc;hb=856b30dae54a9fa76a7457b6c891b3efd9a8a397;hp=690e3628aac0e335f2f0073d6455f3b10311a6fc;hpb=c851a2458fbc12495f4f786d4eabb612850a5143;p=people%2Fms%2Fu-boot.git

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 690e3628aa..e4cc468e72 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -18,21 +18,49 @@ config TARGET_SOCFPGA_CYCLONE5_SOCDK
 	bool "Altera SOCFPGA SoCDK (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_DENX_MCVEVK
+	bool "DENX MCVEVK (Cyclone V)"
+	select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_EBV_SOCRATES
+	bool "EBV SoCrates (Cyclone V)"
+	select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_TERASIC_DE0_NANO
+	bool "Terasic DE0-Nano-Atlas (Cyclone V)"
+	select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_TERASIC_SOCKIT
+	bool "Terasic SoCkit (Cyclone V)"
+	select TARGET_SOCFPGA_CYCLONE5
+
 endchoice
 
 config SYS_BOARD
 	default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
 	default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
+	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
+	default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
+	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
+	default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 
 config SYS_VENDOR
 	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
 	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
+	default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
+	default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
+	default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
+	default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
 
 config SYS_SOC
 	default "socfpga"
 
 config SYS_CONFIG_NAME
-	default "socfpga_arria5" if TARGET_SOCFPGA_ARRIA5_SOCDK
-	default "socfpga_cyclone5" if TARGET_SOCFPGA_CYCLONE5_SOCDK
+	default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+	default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
+	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
+	default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
+	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
+	default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 
 endif