X-Git-Url: http://git.ipfire.org/?a=blobdiff_plain;f=arch%2Fpowerpc%2Fcpu%2Fppc4xx%2Fecc.c;h=88a4605ad5d34f80913038160c05f60fccc66736;hb=d4db3b86a5e090e21db710bedbbe3e50d4c56428;hp=f105605459d5aec6490d70dccc111e8633e23968;hpb=500fbae2043532275e09a8666d837d052c9bad9a;p=people%2Fms%2Fu-boot.git

diff --git a/arch/powerpc/cpu/ppc4xx/ecc.c b/arch/powerpc/cpu/ppc4xx/ecc.c
index f105605459..88a4605ad5 100644
--- a/arch/powerpc/cpu/ppc4xx/ecc.c
+++ b/arch/powerpc/cpu/ppc4xx/ecc.c
@@ -11,23 +11,7 @@
  *    (C) Copyright 2001
  *    Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
  *
- *    See file CREDITS for list of people who contributed to this
- *    project.
- *
- *    This program is free software; you can redistribute it and/or
- *    modify it under the terms of the GNU General Public License as
- *    published by the Free Software Foundation; either version 2 of
- *    the License, or (at your option) any later version.
- *
- *    This program is distributed in the hope that it will abe useful,
- *    but WITHOUT ANY WARRANTY; without even the implied warranty of
- *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- *    GNU General Public License for more details.
- *
- *    You should have received a copy of the GNU General Public License
- *    along with this program; if not, write to the Free Software
- *    Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- *    MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  *
  *    Description:
  *	This file implements generic DRAM ECC initialization for
@@ -37,7 +21,7 @@
  */
 
 #include <common.h>
-#include <ppc4xx.h>
+#include <asm/ppc4xx.h>
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 #include <asm/processor.h>
@@ -130,7 +114,26 @@ static void program_ecc_addr(unsigned long start_address,
 
 		/* clear ECC error repoting registers */
 		mtsdram(SDRAM_ECCES, 0xffffffff);
-		mtdcr(0x4c, 0xffffffff);
+#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)
+		/*
+		 * IBM DDR(1) core (440GX):
+		 * Clear Mx bits in SDRAM0_BESR0/1
+		 */
+		mtsdram(SDRAM0_BESR0, 0xffffffff);
+		mtsdram(SDRAM0_BESR1, 0xffffffff);
+#elif defined(CONFIG_440)
+		/*
+		 * 440/460 DDR2 core:
+		 * Clear EMID (Error PLB Master ID) in MQ0_ESL
+		 */
+		mtdcr(SDRAM_ERRSTATLL, 0xfff00000);
+#else
+		/*
+		 * 405EX(r) DDR2 core:
+		 * Clear M0ID (Error PLB Master ID) in SDRAM_BESR
+		 */
+		mtsdram(SDRAM_BESR, 0xf0000000);
+#endif
 
 		mtsdram(SDRAM_MCOPT1,
 			(mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);