X-Git-Url: http://git.ipfire.org/?a=blobdiff_plain;f=board%2Fatmel%2Fsama5d3xek%2Fsama5d3xek.c;h=ce67478f0be84c99aa63c7f2c45a5e6434077d1c;hb=e856bdcfb49291d30b19603fc101bea096c48196;hp=7c95f33590ed87596ca269b576171ba9bc48cb2c;hpb=89a3658ac02873f32d7ad0a3b1d3c5308c5e2528;p=people%2Fms%2Fu-boot.git

diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c
index 7c95f33590..ce67478f0b 100644
--- a/board/atmel/sama5d3xek/sama5d3xek.c
+++ b/board/atmel/sama5d3xek/sama5d3xek.c
@@ -10,7 +10,6 @@
 #include <asm/io.h>
 #include <asm/arch/sama5d3_smc.h>
 #include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/clk.h>
@@ -69,7 +68,7 @@ void sama5d3xek_nand_hw_init(void)
 }
 #endif
 
-#ifndef CONFIG_SYS_NO_FLASH
+#ifdef CONFIG_MTD_NOR_FLASH
 static void sama5d3xek_nor_hw_init(void)
 {
 	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
@@ -208,7 +207,7 @@ void lcd_show_board_info(void)
 	nand_size = 0;
 #ifdef CONFIG_NAND_ATMEL
 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-		nand_size += nand_info[i].size;
+		nand_size += nand_info[i]->size;
 #endif
 	lcd_printf("%ld MB SDRAM, %lld MB NAND\n",
 		   dram_size >> 20, nand_size >> 20);
@@ -237,7 +236,7 @@ int board_init(void)
 #ifdef CONFIG_NAND_ATMEL
 	sama5d3xek_nand_hw_init();
 #endif
-#ifndef CONFIG_SYS_NO_FLASH
+#ifdef CONFIG_MTD_NOR_FLASH
 	sama5d3xek_nor_hw_init();
 #endif
 #ifdef CONFIG_CMD_USB
@@ -402,7 +401,7 @@ void spl_board_init(void)
 #endif
 }
 
-static void ddr2_conf(struct atmel_mpddr *ddr2)
+static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
 {
 	ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
 
@@ -443,14 +442,13 @@ static void ddr2_conf(struct atmel_mpddr *ddr2)
 
 void mem_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-	struct atmel_mpddr ddr2;
+	struct atmel_mpddrc_config ddr2;
 
 	ddr2_conf(&ddr2);
 
-	/* enable MPDDR clock */
+	/* Enable MPDDR clock */
 	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
-	writel(AT91_PMC_DDR, &pmc->scer);
+	at91_system_clk_enable(AT91_PMC_DDR);
 
 	/* DDRAM2 Controller initialize */
 	ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
@@ -458,7 +456,6 @@ void mem_init(void)
 
 void at91_pmc_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 	u32 tmp;
 
 	tmp = AT91_PMC_PLLAR_29 |
@@ -467,7 +464,7 @@ void at91_pmc_init(void)
 	      AT91_PMC_PLLXR_DIV(1);
 	at91_plla_init(tmp);
 
-	writel(0x3 << 8, &pmc->pllicpr);
+	at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3));
 
 	tmp = AT91_PMC_MCKR_MDIV_4 |
 	      AT91_PMC_MCKR_CSS_PLLA;