X-Git-Url: http://git.ipfire.org/?a=blobdiff_plain;f=board%2Ftqc%2Ftqm8xx%2Ftqm8xx.c;h=489a22c1614fdebbb41313257674c1dc1f13815b;hb=088454cde245b4d431ce0181be8b3cbceea059d6;hp=18bf2a83029c4afedf5a5cbbf5a96b85b4d3088f;hpb=cdeb62e20d94005f2e80604fda03b498c3a6f704;p=people%2Fms%2Fu-boot.git diff --git a/board/tqc/tqm8xx/tqm8xx.c b/board/tqc/tqm8xx/tqm8xx.c index 18bf2a8302..489a22c161 100644 --- a/board/tqc/tqm8xx/tqm8xx.c +++ b/board/tqc/tqm8xx/tqm8xx.c @@ -1,36 +1,23 @@ /* - * (C) Copyright 2000-2006 + * (C) Copyright 2000-2008 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ -#if 0 -#define DEBUG -#endif - #include +#include #include #ifdef CONFIG_PS2MULT #include #endif +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +#include +#endif + +extern flash_info_t flash_info[]; /* FLASH chips info */ + DECLARE_GLOBAL_DATA_PTR; static long int dram_size (long int, long int *, long int); @@ -103,35 +90,35 @@ const uint sdram_table[] = int checkboard (void) { - char *s = getenv ("serial#"); + char buf[64]; + int i; + int l = getenv_f("serial#", buf, sizeof(buf)); puts ("Board: "); - if (!s || strncmp (s, "TQM8", 4)) { + if (l < 0 || strncmp(buf, "TQM8", 4)) { puts ("### No HW ID - assuming TQM8xxL\n"); return (0); } - if ((*(s + 6) == 'L')) { /* a TQM8xxL type */ + if ((buf[6] == 'L')) { /* a TQM8xxL type */ gd->board_type = 'L'; } - if ((*(s + 6) == 'M')) { /* a TQM8xxM type */ + if ((buf[6] == 'M')) { /* a TQM8xxM type */ gd->board_type = 'M'; } - if ((*(s + 6) == 'D')) { /* a TQM885D type */ + if ((buf[6] == 'D')) { /* a TQM885D type */ gd->board_type = 'D'; } - for (; *s; ++s) { - if (*s == ' ') + for (i = 0; i < l; ++i) { + if (buf[i] == ' ') break; - putc (*s); + putc (buf[i]); } -#ifdef CONFIG_VIRTLAB2 - puts (" (Virtlab2)"); -#endif + putc ('\n'); return (0); @@ -139,13 +126,14 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int initdram (int board_type) +int initdram(void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size8, size9, size10; long int size_b0 = 0; long int size_b1 = 0; + int board_type = gd->board_type; upmconfig (UPMA, (uint *) sdram_table, sizeof (sdram_table) / sizeof (uint)); @@ -156,7 +144,7 @@ long int initdram (int board_type) * with two SDRAM banks or four cycles every 31.2 us with one * bank. It will be adjusted after memory sizing. */ - memctl->memc_mptpr = CFG_MPTPR_2BK_8K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K; /* * The following value is used as an address (i.e. opcode) for @@ -178,19 +166,19 @@ long int initdram (int board_type) * preliminary addresses - these have to be modified after the * SDRAM size has been determined. */ - memctl->memc_or2 = CFG_OR2_PRELIM; - memctl->memc_br2 = CFG_BR2_PRELIM; + memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; + memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; #ifndef CONFIG_CAN_DRIVER if ((board_type != 'L') && (board_type != 'M') && (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */ - memctl->memc_or3 = CFG_OR3_PRELIM; - memctl->memc_br3 = CFG_BR3_PRELIM; + memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; + memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; } #endif /* CONFIG_CAN_DRIVER */ - memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ udelay (200); @@ -221,7 +209,7 @@ long int initdram (int board_type) * * try 8 column mode */ - size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); + size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20); udelay (1000); @@ -229,30 +217,30 @@ long int initdram (int board_type) /* * try 9 column mode */ - size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); + size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20); udelay(1000); -#if defined(CFG_MAMR_10COL) +#if defined(CONFIG_SYS_MAMR_10COL) /* * try 10 column mode */ - size10 = dram_size (CFG_MAMR_10COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); + size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); debug ("SDRAM Bank 0 in 10 column mode: %ld MB\n", size10 >> 20); #else size10 = 0; -#endif /* CFG_MAMR_10COL */ +#endif /* CONFIG_SYS_MAMR_10COL */ if ((size8 < size10) && (size9 < size10)) { size_b0 = size10; } else if ((size8 < size9) && (size10 < size9)) { size_b0 = size9; - memctl->memc_mamr = CFG_MAMR_9COL; + memctl->memc_mamr = CONFIG_SYS_MAMR_9COL; udelay (500); } else { size_b0 = size8; - memctl->memc_mamr = CFG_MAMR_8COL; + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; udelay (500); } debug ("SDRAM Bank 0: %ld MB\n", size_b0 >> 20); @@ -283,7 +271,7 @@ long int initdram (int board_type) */ if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) { /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CFG_MPTPR_2BK_4K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; udelay (1000); } @@ -292,15 +280,15 @@ long int initdram (int board_type) */ if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */ - memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; + memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; if (size_b0 > 0) { /* * Position Bank 0 immediately above Bank 1 */ - memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) + memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; + memctl->memc_br2 = ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) + size_b1; } else { unsigned long reg; @@ -314,24 +302,24 @@ long int initdram (int board_type) /* adjust refresh rate depending on SDRAM type, one bank */ reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ memctl->memc_mptpr = reg; } } else { /* SDRAM Bank 0 is bigger - map first */ - memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; memctl->memc_br2 = - (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; if (size_b1 > 0) { /* * Position Bank 1 immediately above Bank 0 */ memctl->memc_or3 = - ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; memctl->memc_br3 = - ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) + ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) + size_b0; } else { unsigned long reg; @@ -347,7 +335,7 @@ long int initdram (int board_type) /* adjust refresh rate depending on SDRAM type, one bank */ reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ memctl->memc_mptpr = reg; } } @@ -358,8 +346,8 @@ long int initdram (int board_type) /* UPM initialization for CAN @ CLKOUT <= 66 MHz */ /* Initialize OR3 / BR3 */ - memctl->memc_or3 = CFG_OR3_CAN; - memctl->memc_br3 = CFG_BR3_CAN; + memctl->memc_or3 = CONFIG_SYS_OR3_CAN; + memctl->memc_br3 = CONFIG_SYS_BR3_CAN; /* Initialize MBMR */ memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */ @@ -399,12 +387,12 @@ long int initdram (int board_type) #ifdef CONFIG_ISP1362_USB /* Initialize OR5 / BR5 */ - memctl->memc_or5 = CFG_OR5_ISP1362; - memctl->memc_br5 = CFG_BR5_ISP1362; + memctl->memc_or5 = CONFIG_SYS_OR5_ISP1362; + memctl->memc_br5 = CONFIG_SYS_BR5_ISP1362; #endif /* CONFIG_ISP1362_USB */ + gd->ram_size = size_b0 + size_b1; - - return (size_b0 + size_b1); + return 0; } /* ------------------------------------------------------------------------- */ @@ -419,7 +407,7 @@ long int initdram (int board_type) static long int dram_size (long int mamr_value, long int *base, long int maxsize) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; memctl->memc_mamr = mamr_value; @@ -429,51 +417,111 @@ static long int dram_size (long int mamr_value, long int *base, long int maxsize /* ------------------------------------------------------------------------- */ -#ifdef CONFIG_PS2MULT +#ifdef CONFIG_MISC_INIT_R +extern void load_sernum_ethaddr(void); +int misc_init_r (void) +{ + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; -#ifdef CONFIG_HMI10 -#define BASE_BAUD ( 1843200 / 16 ) -struct serial_state rs_table[] = { - { BASE_BAUD, 4, (void*)0xec140000 }, - { BASE_BAUD, 2, (void*)0xec150000 }, - { BASE_BAUD, 6, (void*)0xec160000 }, - { BASE_BAUD, 10, (void*)0xec170000 }, -}; + load_sernum_ethaddr(); -#ifdef CONFIG_BOARD_EARLY_INIT_R -int board_early_init_r (void) -{ - ps2mult_early_init(); - return (0); -} +#ifdef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ + int scy, trlx, flash_or_timing, clk_diff; + + scy = (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4; + if (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) { + trlx = OR_TRLX; + scy *= 2; + } else { + trlx = 0; + } + + /* + * We assume that each 10MHz of bus clock require 1-clk SCY + * adjustment. + */ + clk_diff = (gd->bus_clk / 1000000) - 50; + + /* + * We need proper rounding here. This is what the "+5" and "-5" + * are here for. + */ + if (clk_diff >= 0) + scy += (clk_diff + 5) / 10; + else + scy += (clk_diff - 5) / 10; + + /* + * For bus frequencies above 50MHz, we want to use relaxed timing + * (OR_TRLX). + */ + if (gd->bus_clk >= 50000000) + trlx = OR_TRLX; + else + trlx = 0; + + if (trlx) + scy /= 2; + + if (scy > 0xf) + scy = 0xf; + if (scy < 1) + scy = 1; + + flash_or_timing = (scy << 4) | trlx | + (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK)); + + memctl->memc_or0 = + flash_or_timing | (-flash_info[0].size & OR_AM_MSK); +#else + memctl->memc_or0 = + CONFIG_SYS_OR_TIMING_FLASH | (-flash_info[0].size & OR_AM_MSK); #endif -#endif /* CONFIG_HMI10 */ + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; -#endif /* CONFIG_PS2MULT */ + debug ("## BR0: 0x%08x OR0: 0x%08x\n", + memctl->memc_br0, memctl->memc_or0); -/* ---------------------------------------------------------------------------- */ -/* HMI10 specific stuff */ -/* ---------------------------------------------------------------------------- */ -#ifdef CONFIG_HMI10 + if (flash_info[1].size) { +#ifdef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ + memctl->memc_or1 = flash_or_timing | + (-flash_info[1].size & 0xFFFF8000); +#else + memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | + (-flash_info[1].size & 0xFFFF8000); +#endif + memctl->memc_br1 = + ((CONFIG_SYS_FLASH_BASE + + flash_info[0]. + size) & BR_BA_MSK) | BR_MS_GPCM | BR_V; -int misc_init_r (void) -{ -# ifdef CONFIG_IDE_LED - volatile immap_t *immap = (immap_t *) CFG_IMMR; + debug ("## BR1: 0x%08x OR1: 0x%08x\n", + memctl->memc_br1, memctl->memc_or1); + } else { + memctl->memc_br1 = 0; /* invalidate bank */ + debug ("## DISABLE BR1: 0x%08x OR1: 0x%08x\n", + memctl->memc_br1, memctl->memc_or1); + } + +# ifdef CONFIG_IDE_LED /* Configure PA15 as output port */ immap->im_ioport.iop_padir |= 0x0001; immap->im_ioport.iop_paodr |= 0x0001; immap->im_ioport.iop_papar &= ~0x0001; immap->im_ioport.iop_padat &= ~0x0001; /* turn it off */ # endif + return (0); } +#endif /* CONFIG_MISC_INIT_R */ + # ifdef CONFIG_IDE_LED void ide_led (uchar led, uchar status) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; /* We have one led for both pcmcia slots */ if (status) { /* led on */ @@ -483,72 +531,147 @@ void ide_led (uchar led, uchar status) } } # endif -#endif /* CONFIG_HMI10 */ -/* ---------------------------------------------------------------------------- */ -/* NSCU specific stuff */ -/* ---------------------------------------------------------------------------- */ -#ifdef CONFIG_NSCU +#ifdef CONFIG_LCD_INFO +#include +#include +#include -int misc_init_r (void) +void lcd_show_board_info(void) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; - - /* wake up ethernet module */ - immr->im_ioport.iop_pcpar &= ~0x0004; /* GPIO pin */ - immr->im_ioport.iop_pcdir |= 0x0004; /* output */ - immr->im_ioport.iop_pcso &= ~0x0004; /* for clarity */ - immr->im_ioport.iop_pcdat |= 0x0004; /* enable */ + char temp[32]; + + lcd_printf ("%s (%s - %s)\n", U_BOOT_VERSION, U_BOOT_DATE, U_BOOT_TIME); + lcd_printf ("(C) 2008 DENX Software Engineering GmbH\n"); + lcd_printf (" Wolfgang DENK, wd@denx.de\n"); +#ifdef CONFIG_LCD_INFO_BELOW_LOGO + lcd_printf ("MPC823 CPU at %s MHz\n", + strmhz(temp, gd->cpu_clk)); + lcd_printf (" %ld MB RAM, %ld MB Flash\n", + gd->ram_size >> 20, + gd->bd->bi_flashsize >> 20 ); +#else + /* leave one blank line */ + lcd_printf ("\nMPC823 CPU at %s MHz, %ld MB RAM, %ld MB Flash\n", + strmhz(temp, gd->cpu_clk), + gd->ram_size >> 20, + gd->bd->bi_flashsize >> 20 ); +#endif /* CONFIG_LCD_INFO_BELOW_LOGO */ +} +#endif /* CONFIG_LCD_INFO */ - return (0); +/* + * Device Tree Support + */ +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +int fdt_set_node_and_value (void *blob, + char *nodename, + char *regname, + void *var, + int size) +{ + int ret = 0; + int nodeoffset = 0; + + nodeoffset = fdt_path_offset (blob, nodename); + if (nodeoffset >= 0) { + ret = fdt_setprop (blob, nodeoffset, regname, var, + size); + if (ret < 0) { + printf("ft_blob_update(): " + "cannot set %s/%s property; err: %s\n", + nodename, regname, fdt_strerror (ret)); + } + } else { + printf("ft_blob_update(): " + "cannot find %s node err:%s\n", + nodename, fdt_strerror (nodeoffset)); + } + return ret; } -#endif /* CONFIG_NSCU */ - -/* ---------------------------------------------------------------------------- */ -/* TK885D specific initializaion */ -/* ---------------------------------------------------------------------------- */ -#ifdef CONFIG_TK885D -#include -int last_stage_init(void) + +int fdt_del_node_name (void *blob, char *nodename) { - const unsigned char phy[] = {CONFIG_FEC1_PHY, CONFIG_FEC2_PHY}; - unsigned short reg; - int ret, i = 100; - char *s; - - mii_init(); - /* Without this delay 0xff is read from the UART buffer later in - * abortboot() and autoboot is aborted */ - udelay(10000); - while (tstc() && i--) - (void)getc(); - - /* Check if auto-negotiation is prohibited */ - s = getenv("phy_auto_nego"); - - if (!s || !strcmp(s, "on")) - /* Nothing to do - autonegotiation by default */ - return 0; - - for (i = 0; i < 2; i++) { - ret = miiphy_read("FEC ETHERNET", phy[i], PHY_BMCR, ®); - if (ret) { - printf("Cannot read BMCR on PHY %d\n", phy[i]); - return 0; + int ret = 0; + int nodeoffset = 0; + + nodeoffset = fdt_path_offset (blob, nodename); + if (nodeoffset >= 0) { + ret = fdt_del_node (blob, nodeoffset); + if (ret < 0) { + printf("%s: cannot delete %s; err: %s\n", + __func__, nodename, fdt_strerror (ret)); } - /* Auto-negotiation off, hard set full duplex, 100Mbps */ - ret = miiphy_write("FEC ETHERNET", phy[i], - PHY_BMCR, (reg | PHY_BMCR_100MB | - PHY_BMCR_DPLX) & ~PHY_BMCR_AUTON); - if (ret) { - printf("Cannot write BMCR on PHY %d\n", phy[i]); - return 0; + } else { + printf("%s: cannot find %s node err:%s\n", + __func__, nodename, fdt_strerror (nodeoffset)); + } + return ret; +} + +int fdt_del_prop_name (void *blob, char *nodename, char *propname) +{ + int ret = 0; + int nodeoffset = 0; + + nodeoffset = fdt_path_offset (blob, nodename); + if (nodeoffset >= 0) { + ret = fdt_delprop (blob, nodeoffset, propname); + if (ret < 0) { + printf("%s: cannot delete %s %s; err: %s\n", + __func__, nodename, propname, + fdt_strerror (ret)); } + } else { + printf("%s: cannot find %s node err:%s\n", + __func__, nodename, fdt_strerror (nodeoffset)); } + return ret; +} - return 0; +/* + * update "brg" property in the blob + */ +void ft_blob_update (void *blob, bd_t *bd) +{ + uchar enetaddr[6]; + ulong brg_data = 0; + + /* BRG */ + brg_data = cpu_to_be32(bd->bi_busfreq); + fdt_set_node_and_value(blob, + "/soc/cpm", "brg-frequency", + &brg_data, sizeof(brg_data)); + + /* MAC addr */ + if (eth_getenv_enetaddr("ethaddr", enetaddr)) { + fdt_set_node_and_value(blob, + "ethernet0", "local-mac-address", + enetaddr, sizeof(u8) * 6); + } + + if (hwconfig_arg_cmp("fec", "off")) { + /* no FEC on this plattform, delete DTS nodes */ + fdt_del_node_name (blob, "ethernet1"); + fdt_del_node_name (blob, "mdio1"); + /* also the aliases entries */ + fdt_del_prop_name (blob, "/aliases", "ethernet1"); + fdt_del_prop_name (blob, "/aliases", "mdio1"); + } else { + /* adjust local-mac-address for FEC ethernet */ + if (eth_getenv_enetaddr("eth1addr", enetaddr)) { + fdt_set_node_and_value(blob, + "ethernet1", "local-mac-address", + enetaddr, sizeof(u8) * 6); + } + } } -#endif +int ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + ft_blob_update(blob, bd); -/* ------------------------------------------------------------------------- */ + return 0; +} +#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */