X-Git-Url: http://git.ipfire.org/?a=blobdiff_plain;f=board%2Fxilinx%2Fzynqmp%2Fzynqmp.c;h=6c8254b9824b2fca5693180f6ce1d67509129b66;hb=88f05a926d52a4b05eac2e325bb600fa83f8eee1;hp=5e22cc54ba69bba6c1fe908b35b25c059592d6ba;hpb=8ebdf9efad9337a4bec65b8b39a48c0c7b39161a;p=thirdparty%2Fu-boot.git diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 5e22cc54ba6..6c8254b9824 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -28,40 +28,96 @@ static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC; static const struct { u32 id; + u32 ver; char *name; } zynqmp_devices[] = { { .id = 0x10, .name = "3eg", }, + { + .id = 0x10, + .ver = 0x2c, + .name = "3cg", + }, { .id = 0x11, .name = "2eg", }, + { + .id = 0x11, + .ver = 0x2c, + .name = "2cg", + }, { .id = 0x20, .name = "5ev", }, + { + .id = 0x20, + .ver = 0x100, + .name = "5eg", + }, + { + .id = 0x20, + .ver = 0x12c, + .name = "5cg", + }, { .id = 0x21, .name = "4ev", }, + { + .id = 0x21, + .ver = 0x100, + .name = "4eg", + }, + { + .id = 0x21, + .ver = 0x12c, + .name = "4cg", + }, { .id = 0x30, .name = "7ev", }, + { + .id = 0x30, + .ver = 0x100, + .name = "7eg", + }, + { + .id = 0x30, + .ver = 0x12c, + .name = "7cg", + }, { .id = 0x38, .name = "9eg", }, + { + .id = 0x38, + .ver = 0x2c, + .name = "9cg", + }, { .id = 0x39, .name = "6eg", }, + { + .id = 0x39, + .ver = 0x2c, + .name = "6cg", + }, { .id = 0x40, .name = "11eg", }, + { /* For testing purpose only */ + .id = 0x50, + .ver = 0x2c, + .name = "15cg", + }, { .id = 0x50, .name = "15eg", @@ -74,6 +130,30 @@ static const struct { .id = 0x59, .name = "17eg", }, + { + .id = 0x61, + .name = "21dr", + }, + { + .id = 0x63, + .name = "23dr", + }, + { + .id = 0x65, + .name = "25dr", + }, + { + .id = 0x64, + .name = "27dr", + }, + { + .id = 0x60, + .name = "28dr", + }, + { + .id = 0x62, + .name = "29dr", + }, }; #endif @@ -95,6 +175,7 @@ int chip_id(unsigned char id) * regs[0][31:0] = status of the operation * regs[0][63:32] = CSU.IDCODE register * regs[1][31:0] = CSU.version register + * regs[1][63:32] = CSU.IDCODE2 register */ switch (id) { case IDCODE: @@ -109,6 +190,11 @@ int chip_id(unsigned char id) regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK; val = regs.regs[1]; break; + case IDCODE2: + regs.regs[1] = lower_32_bits(regs.regs[1]); + regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT; + val = regs.regs[1]; + break; default: printf("%s, Invalid Req:0x%x\n", __func__, id); } @@ -136,11 +222,13 @@ int chip_id(unsigned char id) !defined(CONFIG_SPL_BUILD) static char *zynqmp_get_silicon_idcode_name(void) { - u32 i, id; + u32 i, id, ver; id = chip_id(IDCODE); + ver = chip_id(IDCODE2); + for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) { - if (zynqmp_devices[i].id == id) + if (zynqmp_devices[i].id == id && zynqmp_devices[i].ver == ver) return zynqmp_devices[i].name; } return "unknown"; @@ -149,15 +237,16 @@ static char *zynqmp_get_silicon_idcode_name(void) int board_early_init_f(void) { + int ret = 0; #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP) zynqmp_pmufw_version(); #endif -#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED) - psu_init(); +#if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED) + ret = psu_init(); #endif - return 0; + return ret; } #define ZYNQMP_VERSION_SIZE 9 @@ -172,10 +261,10 @@ int board_init(void) if (current_el() != 3) { static char version[ZYNQMP_VERSION_SIZE]; - strncat(version, "xczu", 4); + strncat(version, "zu", 2); zynqmppl.name = strncat(version, zynqmp_get_silicon_idcode_name(), - ZYNQMP_VERSION_SIZE - 5); + ZYNQMP_VERSION_SIZE - 3); printf("Chip ID:\t%s\n", zynqmppl.name); fpga_init(); fpga_add(fpga_xilinx, &zynqmppl); @@ -189,10 +278,13 @@ int board_early_init_r(void) { u32 val; + if (current_el() != 3) + return 0; + val = readl(&crlapb_base->timestamp_ref_ctrl); val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; - if (current_el() == 3 && !val) { + if (!val) { val = readl(&crlapb_base->timestamp_ref_ctrl); val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; writel(val, &crlapb_base->timestamp_ref_ctrl); @@ -255,13 +347,18 @@ int board_late_init(void) u8 bootmode; const char *mode; char *new_targets; + char *env_targets; + int ret; if (!(gd->flags & GD_FLG_ENV_DEFAULT)) { debug("Saved variables - Skipping\n"); return 0; } - reg = readl(&crlapb_base->boot_mode); + ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, ®); + if (ret) + return -EINVAL; + if (reg >> BOOT_MODE_ALT_SHIFT) reg >>= BOOT_MODE_ALT_SHIFT; @@ -272,23 +369,28 @@ int board_late_init(void) case USB_MODE: puts("USB_MODE\n"); mode = "usb"; + env_set("modeboot", "usb_dfu_spl"); break; case JTAG_MODE: puts("JTAG_MODE\n"); mode = "pxe dhcp"; + env_set("modeboot", "jtagboot"); break; case QSPI_MODE_24BIT: case QSPI_MODE_32BIT: mode = "qspi0"; puts("QSPI_MODE\n"); + env_set("modeboot", "qspiboot"); break; case EMMC_MODE: puts("EMMC_MODE\n"); mode = "mmc0"; + env_set("modeboot", "emmcboot"); break; case SD_MODE: puts("SD_MODE\n"); mode = "mmc0"; + env_set("modeboot", "sdboot"); break; case SD1_LSHFT_MODE: puts("LVL_SHFT_"); @@ -297,13 +399,16 @@ int board_late_init(void) puts("SD_MODE1\n"); #if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1) mode = "mmc1"; + env_set("sdbootdev", "1"); #else mode = "mmc0"; #endif + env_set("modeboot", "sdboot"); break; case NAND_MODE: puts("NAND_MODE\n"); mode = "nand0"; + env_set("modeboot", "nandboot"); break; default: mode = ""; @@ -315,10 +420,16 @@ int board_late_init(void) * One terminating char + one byte for space between mode * and default boot_targets */ - new_targets = calloc(1, strlen(mode) + - strlen(env_get("boot_targets")) + 2); + env_targets = env_get("boot_targets"); + if (env_targets) { + new_targets = calloc(1, strlen(mode) + + strlen(env_targets) + 2); + sprintf(new_targets, "%s %s", mode, env_targets); + } else { + new_targets = calloc(1, strlen(mode) + 2); + sprintf(new_targets, "%s", mode); + } - sprintf(new_targets, "%s %s", mode, env_get("boot_targets")); env_set("boot_targets", new_targets); return 0;