X-Git-Url: http://git.ipfire.org/?a=blobdiff_plain;f=doc%2FREADME.x86;h=772e8d2a8693b0d8f87277e47a30d95488fe590c;hb=7b1cfec31764cd9247ee3cdaf5b7caa804741344;hp=c542a6965c34b61883a57a31d8f1c9c84562fa6a;hpb=248a3f6c7ce01965f0303416645c8884013acabb;p=people%2Fms%2Fu-boot.git

diff --git a/doc/README.x86 b/doc/README.x86
index c542a6965c..772e8d2a86 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -26,6 +26,7 @@ In this case, known as bare mode, from the fact that it runs on the
 are supported:
 
    - Bayley Bay CRB
+   - Cherry Hill CRB
    - Congatec QEVAL 2.0 & conga-QA3/E3845
    - Cougar Canyon 2 CRB
    - Crown Bay CRB
@@ -79,11 +80,15 @@ Building a ROM version of U-Boot (hereafter referred to as u-boot.rom) is a
 little bit tricky, as generally it requires several binary blobs which are not
 shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is
 not turned on by default in the U-Boot source tree. Firstly, you need turn it
-on by enabling the ROM build:
+on by enabling the ROM build either via an environment variable
 
-$ export BUILD_ROM=y
+    $ export BUILD_ROM=y
 
-This tells the Makefile to build u-boot.rom as a target.
+or via configuration
+
+    CONFIG_BUILD_ROM=y
+
+Both tell the Makefile to build u-boot.rom as a target.
 
 ---
 
@@ -319,7 +324,7 @@ Offset   Description         Controlling config
 6ef000   Environment         CONFIG_ENV_OFFSET
 6f0000   MRC cache           CONFIG_ENABLE_MRC_CACHE
 700000   u-boot-dtb.bin      CONFIG_SYS_TEXT_BASE
-790000   vga.bin             CONFIG_VGA_BIOS_ADDR
+7b0000   vga.bin             CONFIG_VGA_BIOS_ADDR
 7c0000   fsp.bin             CONFIG_FSP_ADDR
 7f8000   <spare>             (depends on size of fsp.bin)
 7ff800   U-Boot 16-bit boot  CONFIG_SYS_X86_START16
@@ -332,6 +337,35 @@ the default value 0xfffc0000.
 
 ---
 
+Intel Cherry Hill specific instructions for bare mode:
+
+This uses Intel FSP for Braswell platform. Download it from Intel FSP website,
+put the .fd file to the board directory and rename it to fsp.bin.
+
+Extract descriptor.bin and me.bin from the original BIOS on the board using
+ifdtool and put them to the board directory as well.
+
+Note the FSP package for Braswell does not ship a traditional legacy VGA BIOS
+image for the integrated graphics device. Instead a new binary called Video
+BIOS Table (VBT) is shipped. Put it to the board directory and rename it to
+vbt.bin if you want graphics support in U-Boot.
+
+Now you can build U-Boot and obtain u-boot.rom
+
+$ make cherryhill_defconfig
+$ make all
+
+An important note for programming u-boot.rom to the on-board SPI flash is that
+you need make sure the SPI flash's 'quad enable' bit in its status register
+matches the settings in the descriptor.bin, otherwise the board won't boot.
+
+For the on-board SPI flash MX25U6435F, this can be done by writing 0x40 to the
+status register by DediProg in: Config > Modify Status Register > Write Status
+Register(s) > Register1 Value(Hex). This is is a one-time change. Once set, it
+persists in SPI flash part regardless of the u-boot.rom image burned.
+
+---
+
 Intel Galileo instructions for bare mode:
 
 Only one binary blob is needed for Remote Management Unit (RMU) within Intel