X-Git-Url: http://git.ipfire.org/?a=blobdiff_plain;f=drivers%2Fmmc%2Fbfin_sdh.c;h=81d8e5432f941f94d7eea769bb09f4309d9fd8eb;hb=d23d8d7e069c3aca071b7f68d9c15d11f8d4c84d;hp=4a77779f5b6bfb5bdf20ad92ab52b9fbe53198bd;hpb=a87589fcf9b58b599c5a9b07ab4ecbc42354348d;p=people%2Fms%2Fu-boot.git

diff --git a/drivers/mmc/bfin_sdh.c b/drivers/mmc/bfin_sdh.c
index 4a77779f5b..81d8e5432f 100644
--- a/drivers/mmc/bfin_sdh.c
+++ b/drivers/mmc/bfin_sdh.c
@@ -19,7 +19,7 @@
 #include <asm/mach-common/bits/sdh.h>
 #include <asm/mach-common/bits/dma.h>
 
-#if defined(__ADSPBF51x__)
+#if defined(__ADSPBF50x__) || defined(__ADSPBF51x__)
 # define bfin_read_SDH_PWR_CTL		bfin_read_RSI_PWR_CONTROL
 # define bfin_write_SDH_PWR_CTL		bfin_write_RSI_PWR_CONTROL
 # define bfin_read_SDH_CLK_CTL		bfin_read_RSI_CLK_CONTROL
@@ -58,27 +58,29 @@
 static int
 sdh_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd)
 {
-	unsigned int sdh_cmd;
-	unsigned int status;
+	unsigned int status, timeout;
 	int cmd = mmc_cmd->cmdidx;
 	int flags = mmc_cmd->resp_type;
 	int arg = mmc_cmd->cmdarg;
-	int ret = 0;
-	sdh_cmd = 0;
-
-	sdh_cmd |= cmd;
+	int ret;
+	u16 sdh_cmd;
 
+	sdh_cmd = cmd | CMD_E;
 	if (flags & MMC_RSP_PRESENT)
 		sdh_cmd |= CMD_RSP;
-
 	if (flags & MMC_RSP_136)
 		sdh_cmd |= CMD_L_RSP;
 
 	bfin_write_SDH_ARGUMENT(arg);
-	bfin_write_SDH_COMMAND(sdh_cmd | CMD_E);
+	bfin_write_SDH_COMMAND(sdh_cmd);
 
 	/* wait for a while */
+	timeout = 0;
 	do {
+		if (++timeout > 1000000) {
+			status = CMD_TIME_OUT;
+			break;
+		}
 		udelay(1);
 		status = bfin_read_SDH_STATUS();
 	} while (!(status & (CMD_SENT | CMD_RESP_END | CMD_TIME_OUT |
@@ -94,12 +96,15 @@ sdh_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd)
 	}
 
 	if (status & CMD_TIME_OUT)
-		ret |= TIMEOUT;
+		ret = TIMEOUT;
 	else if (status & CMD_CRC_FAIL && flags & MMC_RSP_CRC)
-		ret |= COMM_ERR;
+		ret = COMM_ERR;
+	else
+		ret = 0;
 
 	bfin_write_SDH_STATUS_CLR(CMD_SENT_STAT | CMD_RESP_END_STAT |
 				CMD_TIMEOUT_STAT | CMD_CRC_FAIL_STAT);
+
 	return ret;
 }
 
@@ -109,25 +114,26 @@ static int sdh_setup_data(struct mmc *mmc, struct mmc_data *data)
 	u16 data_ctl = 0;
 	u16 dma_cfg = 0;
 	int ret = 0;
+	unsigned long data_size = data->blocksize * data->blocks;
 
 	/* Don't support write yet. */
 	if (data->flags & MMC_DATA_WRITE)
 		return UNUSABLE_ERR;
-	data_ctl |= ((ffs(data->blocksize) - 1) << 4);
+	data_ctl |= ((ffs(data_size) - 1) << 4);
 	data_ctl |= DTX_DIR;
 	bfin_write_SDH_DATA_CTL(data_ctl);
 	dma_cfg = WDSIZE_32 | RESTART | WNR | DMAEN;
 
-	bfin_write_SDH_DATA_TIMER(0xFFFF);
+	bfin_write_SDH_DATA_TIMER(-1);
 
 	blackfin_dcache_flush_invalidate_range(data->dest,
-			data->dest + data->blocksize);
+			data->dest + data_size);
 	/* configure DMA */
 	bfin_write_DMA_START_ADDR(data->dest);
-	bfin_write_DMA_X_COUNT(data->blocksize / 4);
+	bfin_write_DMA_X_COUNT(data_size / 4);
 	bfin_write_DMA_X_MODIFY(4);
 	bfin_write_DMA_CONFIG(dma_cfg);
-	bfin_write_SDH_DATA_LGTH(data->blocksize);
+	bfin_write_SDH_DATA_LGTH(data_size);
 	/* kick off transfer */
 	bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E);
 
@@ -244,12 +250,15 @@ int bfin_mmc_init(bd_t *bis)
 	mmc->send_cmd = bfin_sdh_request;
 	mmc->set_ios = bfin_sdh_set_ios;
 	mmc->init = bfin_sdh_init;
+	mmc->getcd = NULL;
+	mmc->getwp = NULL;
 	mmc->host_caps = MMC_MODE_4BIT;
 
 	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 	mmc->f_max = get_sclk();
 	mmc->f_min = mmc->f_max >> 9;
-	mmc->block_dev.part_type = PART_TYPE_DOS;
+
+	mmc->b_max = 0;
 
 	mmc_register(mmc);