X-Git-Url: http://git.ipfire.org/?a=blobdiff_plain;f=gas%2FNEWS;h=36d6c652f6d32a8d466fb6f8e7ef8686b4b5a956;hb=6655dba246bd164d953fe220a0e3d4eed85bb268;hp=c277dad87536670b88807f4c9f40e6812da203e3;hpb=fe13e45b9a7ffd7f0f0f3c88fd76c6be6fabbc66;p=thirdparty%2Fbinutils-gdb.git diff --git a/gas/NEWS b/gas/NEWS index c277dad8753..36d6c652f6d 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,216 @@ -*- text -*- +* Add support for Zilog eZ80 and Zilog Z180 CPUs. + +* Add support for z80-elf target. + +* Add support for relocation of each byte or word of multibyte value to Z80 + targets (just use right shift to 0, 8, 16, or 24 bits or AND operation + with 0xff/0xffff mask): ld a, label >> 16 \ ld hl, label & 0xffff + +* Add SDCC support for Z80 targets. + +Changes in 2.33: + +* Add support for the Arm Scalable Vector Extension version 2 (SVE2) + instructions. + +* Add support for the Arm Transactional Memory Extension (TME) + instructions. + +* Add support for the Armv8.1-M Mainline and M-profile Vector Extension (MVE) + instructions. + +* For MIPS, Add -m[no-]fix-loongson3-llsc option to fix (or not) Loongson3 + LLSC Errata. Add a --enable-mips-fix-loongson3-llsc=[yes|no] configure + time option to set the default behavior. Set the default if the configure + option is not used to "no". + +* Add support for the Arm Cortex-A76AE, Cortex-A77 and Cortex-M35P + processors. + +* Add support for the AArch64 Cortex-A34, Cortex-A65, Cortex-A65AE, + Cortex-A76AE, and Cortex-A77 processors. + +* Add .float16 directive for both Arm and AArch64 to allow encoding of 16-bit + floating point literals. Add .float16_format directive and + -mfp16-format=[ieee|alternative] option for Arm to control the format of the + encoding. + +* Add --gdwarf-cie-version command line flag. This allows control over which + version of DWARF CIE the assembler creates. + +Changes in 2.32: + +* Add -mvexwig=[0|1] option to x86 assembler to control encoding of + VEX.W-ignored (WIG) VEX instructions. + +* Add -mx86-used-note=[yes|no] option to generate (or not) x86 GNU property + notes. Add a --enable-x86-used-note configure time option to set the + default behavior. Set the default if the configure option is not used + to "no". + +* Add support for the MIPS Loongson EXTensions R2 (EXT2) instructions. + +* Add support for the MIPS Loongson EXTensions (EXT) instructions. + +* Add support for the MIPS Loongson Content Address Memory (CAM) ASE. + +* Add support for the C-SKY processor series. + +* Add support for the MIPS Loongson MultiMedia extensions Instructions (MMI) + ASE. + +Changes in 2.31: + +* The ADR and ADRL pseudo-instructions supported by the ARM assembler + now only set the bottom bit of the address of thumb function symbols + if the -mthumb-interwork command line option is active. + +* Add support for the MIPS Global INValidate (GINV) ASE. + +* Add support for the MIPS Cyclic Redudancy Check (CRC) ASE. + +* Add support for the Freescale S12Z architecture. + +* Add --generate-missing-build-notes=[yes|no] option to create (or not) GNU + Build Attribute notes if none are present in the input sources. Add a + --enable-generate-build-notes=[yes|no] configure time option to set the + default behaviour. Set the default if the configure option is not used + to "no". + +* Remove -mold-gcc command-line option for x86 targets. + +* Add -O[2|s] command-line options to x86 assembler to enable alternate + shorter instruction encoding. + +* Add support for .nops directive. It is currently supported only for + x86 targets. + +Changes in 2.30: + +* Add support for loaction views in DWARF debug line information. + +Changes in 2.29: + +* Add support for ELF SHF_GNU_MBIND. + +* Add support for the WebAssembly file format and wasm32 ELF conversion. + +* PowerPC gas now checks that the correct register class is used in + instructions. For instance, "addi %f4,%cr3,%r31" warns three times + that the registers are invalid. + +* Add support for the Texas Instruments PRU processor. + +* Support for the ARMv8-R architecture and Cortex-R52 processor has been + added to the ARM port. + +Changes in 2.28: + +* Add support for the RISC-V architecture. + +* Add support for the ARM Cortex-M23 and Cortex-M33 processors. + +Changes in 2.27: + +* Default to --enable-compressed-debug-sections=gas for Linux/x86 targets. + +* Add --no-pad-sections to stop the assembler from padding the end of output + sections up to their alignment boundary. + +* Support for the ARMv8-M architecture has been added to the ARM port. Support + for the ARMv8-M Security and DSP Extensions has also been added to the ARM + port. + +* ARC backend accepts .extInstruction, .extCondCode, .extAuxRegister, and + .extCoreRegister pseudo-ops that allow an user to define custom + instructions, conditional codes, auxiliary and core registers. + +* Add a configure option --enable-elf-stt-common to decide whether ELF + assembler should generate common symbols with the STT_COMMON type by + default. Default to no. + +* New command-line option --elf-stt-common= for ELF targets to control + whether to generate common symbols with the STT_COMMON type. + +* Add ability to set section flags and types via numeric values for ELF + based targets. + +* Add a configure option --enable-x86-relax-relocations to decide whether + x86 assembler should generate relax relocations by default. Default to + yes, except for x86 Solaris targets older than Solaris 12. + +* New command-line option -mrelax-relocations= for x86 target to control + whether to generate relax relocations. + +* New command-line option -mfence-as-lock-add=yes for x86 target to encode + lfence, mfence and sfence as "lock addl $0x0, (%[re]sp)". + +* Add assembly-time relaxation option for ARC cpus. + +* Add --with-cpu=TYPE configure option for ARC gas. This allows the default + cpu type to be adjusted at configure time. + +Changes in 2.26: + +* Add a configure option --enable-compressed-debug-sections={all,gas} to + decide whether DWARF debug sections should be compressed by default. + +* Add support for the ARC EM/HS, and ARC600/700 architectures. Remove + assembler support for Argonaut RISC architectures. + +* Symbol and label names can now be enclosed in double quotes (") which allows + them to contain characters that are not part of valid symbol names in high + level languages. + +* Added the correctly spelled -march=armv6kz, for ARMv6KZ support. The + previous spelling, -march=armv6zk, is still accepted. + +* Support for the ARMv8.1 architecture has been added to the Aarch64 port. + Support for the individual ARMv8.1 Adv.SIMD, LOR and PAN architecture + extensions has also been added to the Aarch64 port. + +* Support for the ARMv8.1 architecture has been added to the ARM port. Support + for the individual ARMv8.1 Adv.SIMD and PAN architecture extensions has also + been added to the ARM port. + +* Extend --compress-debug-sections option to support + --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi] for ELF + targets. + +* --compress-debug-sections is turned on for Linux/x86 by default. + +Changes in 2.25: + +* Add support for the AVR Tiny microcontrollers. + +* Replace support for openrisc and or32 with support for or1k. + +* Enhanced the ARM port to accept the assembler output from the CodeComposer + Studio tool. Support is enabled via the new command-line option -mccs. + +* Add support for the Andes NDS32. + +Changes in 2.24: + +* Add support for the Texas Instruments MSP430X processor. + +* Add -gdwarf-sections command-line option to enable per-code-section + generation of DWARF .debug_line sections. + +* Add support for Altera Nios II. + +* Add support for the Imagination Technologies Meta processor. + +* Add support for the v850e3v5. + +* Remove assembler support for MIPS ECOFF targets. + +Changes in 2.23: + +* Add support for the 64-bit ARM architecture: AArch64. + * Add support for S12X processor. * Add support for the VLE extension to the PowerPC architecture. @@ -32,7 +243,7 @@ Changes in 2.21: * Add support for the Renesas RX processor. -* New command line option, --compress-debug-sections, which requests +* New command-line option, --compress-debug-sections, which requests compression of DWARF debug information sections in the relocatable output file. Compressed debug sections are supported by readelf, objdump, and gold, but not currently by Gnu ld. @@ -69,23 +280,23 @@ Changes in 2.19: * New pseudo op .cfi_val_encoded_addr, to record constant addresses in unwind tables without runtime relocation. -* New command line option, -h-tick-hex, for sh, m32c, and h8/300 targets, which +* New command-line option, -h-tick-hex, for sh, m32c, and h8/300 targets, which adds compatibility with H'00 style hex constants. -* New command line option, -msse-check=[none|error|warning], for x86 +* New command-line option, -msse-check=[none|error|warning], for x86 targets. -* New sub-option added to the assembler's -a command line switch to +* New sub-option added to the assembler's -a command-line switch to generate a listing output. The 'g' sub-option will insert into the listing various information about the assembly, such as assembler version, the - command line options used, and a time stamp. + command-line options used, and a time stamp. -* New command line option -msse2avx for x86 target to encode SSE +* New command-line option -msse2avx for x86 target to encode SSE instructions with VEX prefix. * Add Intel XSAVE, EPT, MOVBE, AES, PCLMUL, AVX/FMA support for x86 target. -* New command line options, -march=CPU[,+EXTENSION...], -mtune=CPU, +* New command-line options, -march=CPU[,+EXTENSION...], -mtune=CPU, -mmnemonic=[att|intel], -msyntax=[att|intel], -mindex-reg, -mnaked-reg and -mold-gcc, for x86 targets. @@ -118,7 +329,7 @@ Changes in 2.17: * Add support for the "@" syntax to the command line, so that extra switches can be read from . -* The SH target supports a new command line switch --enable-reg-prefix which, +* The SH target supports a new command-line switch --enable-reg-prefix which, if enabled, will allow register names to be optionally prefixed with a $ character. This allows register names to be distinguished from label names. @@ -139,15 +350,15 @@ Changes in 2.17: for the VAX target in order to be more compatible with the VAX MACRO assembler. -* New command line option -mtune=[itanium1|itanium2] for IA64 targets. +* New command-line option -mtune=[itanium1|itanium2] for IA64 targets. Changes in 2.16: * Redefinition of macros now results in an error. -* New command line option -mhint.b=[ok|warning|error] for IA64 targets. +* New command-line option -mhint.b=[ok|warning|error] for IA64 targets. -* New command line option -munwind-check=[warning|error] for IA64 +* New command-line option -munwind-check=[warning|error] for IA64 targets. * The IA64 port now uses automatic dependency violation removal as its default @@ -157,7 +368,7 @@ Changes in 2.16: * Added support for generating unwind tables for ARM ELF targets. -* Add a -g command line option to generate debug information in the target's +* Add a -g command-line option to generate debug information in the target's preferred debug format. * Support for the crx-elf target added. @@ -172,9 +383,9 @@ Changes in 2.16: * Support for ColdFire EMAC instructions added and Motorola syntax for MAC/EMAC instrucitons. -* New command line option -mno-shared for MIPS ELF targets. +* New command-line option -mno-shared for MIPS ELF targets. -* New command line option --alternate and pseudo-ops .altmacro and .noaltmacro +* New command-line option --alternate and pseudo-ops .altmacro and .noaltmacro added to enter (and leave) alternate macro syntax mode. Changes in 2.15: @@ -268,7 +479,7 @@ Changes in 2.12: but still works for compatability. * The MIPS assembler no longer issues a warning by default when it - generates a nop instruction from a macro. The new command line option + generates a nop instruction from a macro. The new command-line option -n will turn on the warning. Changes in 2.11: @@ -291,7 +502,7 @@ Changes in 2.11: * x86 gas has a new .arch pseudo op to specify the target CPU architecture. -* x86 gas -q command line option quietens warnings about register size changes +* x86 gas -q command-line option quietens warnings about register size changes due to suffix, indirect jmp/call without `*', stand-alone prefixes, and translating various deprecated floating point instructions. @@ -596,6 +807,12 @@ Changes in 1.93.01: of new CPUs and formats, lots of bugs fixed. +Copyright (C) 2012-2020 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright +notice and this notice are preserved. + Local variables: fill-column: 79 End: