X-Git-Url: http://git.ipfire.org/?a=blobdiff_plain;f=include%2Fconfigs%2Fam3517_evm.h;h=c0d3617acac20c44cbca237c274f6a7571f2b3b7;hb=1d2c0506d31a9997e5ffc22e90942902f673b107;hp=70490910d7396c2b80881561523e0b8753c526e4;hpb=7c0e5d865ff0b86dfce492b656238919c659d756;p=people%2Fms%2Fu-boot.git diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 70490910d7..c0d3617aca 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -13,13 +13,14 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* - * High Level Configuration Options - */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP3_AM3517EVM 1 /* working with AM3517EVM */ -#define CONFIG_OMAP_COMMON -#define CONFIG_SYS_GENERIC_BOARD +/* High Level Configuration Options */ + +#define CONFIG_OMAP + +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ + /* Common ARM Erratas */ #define CONFIG_ARM_ERRATA_454179 #define CONFIG_ARM_ERRATA_430973 @@ -27,60 +28,44 @@ #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. + */ +#define CONFIG_SYS_TEXT_BASE 0x80100000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + #include /* get chip and board defs */ #include -/* - * Display CPU and Board information - */ -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 +#define CONFIG_MISC_INIT_R +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG /* Clock Defines */ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK >> 1) -#define CONFIG_MISC_INIT_R - -#define CONFIG_OF_LIBFDT +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 << 20) -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_REVISION_TAG 1 +/* Hardware drivers */ -/* - * Size of malloc() pool - */ -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) -/* - * DDR related - */ -#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) - -/* - * Hardware drivers - */ - -/* - * OMAP GPIO configuration - */ +/* OMAP GPIO configuration */ #define CONFIG_OMAP_GPIO -/* - * NS16550 Configuration - */ +/* NS16550 Configuration */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ - -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK -/* - * select serial console configuration - */ +/* select serial console configuration */ #define CONFIG_CONS_INDEX 3 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 #define CONFIG_SERIAL3 3 /* UART3 on AM3517 EVM */ @@ -90,10 +75,10 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 115200} -#define CONFIG_MMC 1 -#define CONFIG_GENERIC_MMC 1 -#define CONFIG_OMAP_HSMMC 1 -#define CONFIG_DOS_PARTITION 1 + +/* SD/MMC */ +#define CONFIG_GENERIC_MMC +#define CONFIG_DOS_PARTITION /* * USB configuration @@ -101,17 +86,13 @@ * Enable CONFIG_USB_MUSB_GADGET for Device functionalities. */ #define CONFIG_USB_MUSB_AM35X -#define CONFIG_USB_MUSB_HOST #define CONFIG_USB_MUSB_PIO_ONLY #ifdef CONFIG_USB_MUSB_AM35X #ifdef CONFIG_USB_MUSB_HOST -#define CONFIG_CMD_USB -#define CONFIG_USB_STORAGE #define CONGIG_CMD_STORAGE -#define CONFIG_CMD_FAT #ifdef CONFIG_USB_KEYBOARD #define CONFIG_SYS_USB_EVENT_POLL @@ -121,7 +102,6 @@ #endif /* CONFIG_USB_MUSB_HOST */ #ifdef CONFIG_USB_MUSB_GADGET -#define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_ETHER #define CONFIG_USB_ETH_RNDIS #endif /* CONFIG_USB_MUSB_GADGET */ @@ -129,26 +109,17 @@ #endif /* CONFIG_USB_MUSB_AM35X */ /* commands to include */ -#define CONFIG_CMD_EXT2 /* EXT2 Support */ -#define CONFIG_CMD_FAT /* FAT support */ -#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ - -#define CONFIG_CMD_I2C /* I2C serial bus support */ -#define CONFIG_CMD_MMC /* MMC support */ -#define CONFIG_CMD_NAND /* NAND support */ -#define CONFIG_CMD_DHCP -#undef CONFIG_CMD_PING - +#define CONFIG_CMD_NAND +#define CONFIG_CMD_PART +#define CONFIG_CMD_MTDPARTS -#define CONFIG_SYS_NO_FLASH +/* I2C */ #define CONFIG_SYS_I2C #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 #define CONFIG_SYS_I2C_OMAP34XX -/* - * Ethernet - */ +/* Ethernet */ #define CONFIG_DRIVER_TI_EMAC #define CONFIG_DRIVER_TI_EMAC_USE_RMII #define CONFIG_MII @@ -158,76 +129,149 @@ #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_NET_RETRY_COUNT 10 -/* - * Board NAND Info. - */ +/* Board NAND Info. */ +#ifdef CONFIG_NAND +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_NAND_OMAP_GPMC_PREFETCH +#define CONFIG_BCH +#define CONFIG_CMD_UBIFS /* Read-only UBI volume operations */ +#define CONFIG_RBTREE /* required by CONFIG_CMD_UBI */ +#define CONFIG_LZO /* required by CONFIG_CMD_UBIFS */ #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ /* to access nand */ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access */ /* nand at CS0 */ - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ /* NAND devices */ -#define CONFIG_JFFS2_NAND -/* nand device jffs2 lives on */ -#define CONFIG_JFFS2_DEV "nand0" -/* start of jffs2 partition */ -#define CONFIG_JFFS2_PART_OFFSET 0x680000 -#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, 10, \ + 11, 12, 13, 14, 16, 17, 18, 19, 20, \ + 21, 22, 23, 24, 25, 26, 27, 28, 30, \ + 31, 32, 33, 34, 35, 36, 37, 38, 39, \ + 40, 41, 42, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56 } + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 13 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW +#define CONFIG_SYS_NAND_MAX_OOBFREE 2 +#define CONFIG_SYS_NAND_MAX_ECCPOS 56 +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +#define CONFIG_MTD_PARTITIONS /* required for UBI partition support */ +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +/* NAND block size is 128 KiB. Synchronize these values with + * corresponding Device Tree entries in Linux: + * MLO(SPL) 4 * NAND_BLOCK_SIZE = 512 KiB @ 0x000000 + * U-Boot 15 * NAND_BLOCK_SIZE = 1920 KiB @ 0x080000 + * U-Boot environment 2 * NAND_BLOCK_SIZE = 256 KiB @ 0x260000 + * Kernel 64 * NAND_BLOCK_SIZE = 8 MiB @ 0x2A0000 + * DTB 4 * NAND_BLOCK_SIZE = 512 KiB @ 0xAA0000 + * RootFS Remaining Flash Space @ 0xB20000 + */ +#define MTDIDS_DEFAULT "nand0=omap2-nand.0" +#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \ + "512k(MLO)," \ + "1920k(u-boot)," \ + "256k(u-boot-env)," \ + "8m(kernel)," \ + "512k(dtb)," \ + "-(rootfs)" +#else +#define MTDIDS_DEFAULT +#define MTDPARTS_DEFAULT +#endif /* CONFIG_NAND */ /* Environment information */ -#define CONFIG_BOOTDELAY 10 #define CONFIG_BOOTFILE "uImage" #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ "console=ttyO2,115200n8\0" \ + "fdtfile=am3517-evm.dtb\0" \ + "fdtaddr=0x82C00000\0" \ + "vram=16M\0" \ + "bootenv=uEnv.txt\0" \ + "cmdline=\0" \ + "optargs=\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ "mmcdev=0\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ + "mmcrootfstype=ext4 rootwait fixrtc\0" \ "mmcargs=setenv bootargs console=${console} " \ - "root=/dev/mmcblk0p2 rw rootwait\0" \ + "${mtdparts} " \ + "${optargs} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype} " \ + "${cmdline}\0" \ "nandargs=setenv bootargs console=${console} " \ - "root=/dev/mtdblock4 rw " \ - "rootfstype=jffs2\0" \ - "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "${mtdparts} " \ + "${optargs} " \ + "root=ubi0:rootfs rw ubi.mtd=rootfs " \ + "rootfstype=ubifs rootwait " \ + "${cmdline}\0" \ + "loadbootenv=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bootenv}\0"\ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t ${loadaddr} ${filesize}\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source ${loadaddr}\0" \ - "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bootfile}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdtaddr} ${fdtfile}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ - "bootm ${loadaddr}\0" \ + "bootz ${loadaddr} - ${fdtaddr}\0" \ "nandboot=echo Booting from nand ...; " \ "run nandargs; " \ - "nand read ${loadaddr} 280000 400000; " \ - "bootm ${loadaddr}\0" \ + "nand read ${loadaddr} 2a0000 800000; " \ + "nand read ${fdtaddr} aa0000 80000; " \ + "bootm ${loadaddr} - ${fdtaddr}\0" \ #define CONFIG_BOOTCOMMAND \ "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "else run nandboot; " \ - "fi; " \ + "echo SD/MMC found on device $mmcdev; " \ + "if run loadbootenv; then " \ + "run importbootenv; " \ + "fi; " \ + "echo Checking if uenvcmd is set ...; " \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...; " \ + "run uenvcmd; " \ + "fi; " \ + "echo Running default loadimage ...; " \ + "setenv bootfile zImage; " \ + "if run loadimage; then " \ + "run loadfdt; " \ + "run mmcboot; " \ "fi; " \ "else run nandboot; fi" -#define CONFIG_AUTO_COMPLETE 1 -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +/* Miscellaneous configurable options */ +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP +#define CONFIG_PARTITION_UUIDS + +/* We set the max number of command args high to avoid HUSH bugs. */ +#define CONFIG_SYS_MAXARGS 64 + +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 512 /* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 32 /* max number of command */ - /* args */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + + sizeof(CONFIG_SYS_PROMPT) + 16) /* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* memtest works on */ #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ @@ -244,16 +288,18 @@ #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 +/* Physical Memory Map */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 +#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 +#define CONFIG_SYS_INIT_RAM_SIZE 0x800 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ +/* FLASH and environment organization */ /* **** PISMO SUPPORT *** */ #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ @@ -261,95 +307,37 @@ #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ -#if defined(CONFIG_CMD_NAND) +#if defined(CONFIG_NAND) #define CONFIG_SYS_FLASH_BASE NAND_BASE #endif /* Monitor at start of flash */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_NAND_OMAP_GPMC -#define CONFIG_ENV_IS_IN_NAND 1 -#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ - #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_SIZE CONFIG_SYS_ENV_SECT_SIZE +#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET - -/*----------------------------------------------------------------------- - * CFI FLASH driver setup - */ -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) - -/* Flash banks JFFS2 should use */ -#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ - CONFIG_SYS_MAX_NAND_DEVICE) -#define CONFIG_SYS_JFFS2_MEM_NAND -/* use flash_info[2] */ -#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) +#define CONFIG_ENV_IS_IN_NAND /* Defines for SPL */ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_NAND_SIMPLE -#define CONFIG_SPL_TEXT_BASE 0x40200800 -#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ +#define CONFIG_SPL_TEXT_BASE 0x40200000 +#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ + CONFIG_SPL_TEXT_BASE) #define CONFIG_SPL_BSS_START_ADDR 0x80000000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBDISK_SUPPORT -#define CONFIG_SPL_I2C_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SPL_FAT_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" + #define CONFIG_SPL_NAND_BASE #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_ECC -#define CONFIG_SPL_POWER_SUPPORT -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" - -/* NAND boot config */ -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ - 10, 11, 12, 13} -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 - -/* - * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM - * 64 bytes before this address should be set aside for u-boot.img's - * header. That is 0x800FFFC0--0x80100000 should not be used for any - * other needs. - */ -#define CONFIG_SYS_TEXT_BASE 0x80100000 -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" #endif /* __CONFIG_H */