X-Git-Url: http://git.ipfire.org/?a=blobdiff_plain;f=include%2Fconfigs%2Fomap3_overo.h;h=ebf7dd0c01fbb044cfd00b57071681a6e0222b8e;hb=8435179271106ec6fe9a9a5679b897755b1db8dd;hp=d042eea1b04ccd195e7fe9193a063e5822beba3a;hpb=f2565a551c001f0441dbe51dc31438961fce7b53;p=people%2Fms%2Fu-boot.git

diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index d042eea1b0..ebf7dd0c01 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -11,10 +11,14 @@
 #define CONFIG_NAND
 
 #include <configs/ti_omap3_common.h>
+/*
+ * We are only ever GP parts and will utilize all of the "downloaded image"
+ * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB).
+ */
+#undef CONFIG_SPL_TEXT_BASE
+#define CONFIG_SPL_TEXT_BASE		0x40200000
 
-/* Display CPU and Board information */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BCH
 
 /* call misc_init_r */
 #define CONFIG_MISC_INIT_R
@@ -35,6 +39,12 @@
 /* TWL4030 LED */
 #define CONFIG_TWL4030_LED
 
+/* USB EHCI */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_OMAP
+#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	183
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	3
+
 /* Initialize GPIOs by default */
 #define CONFIG_OMAP3_GPIO_2	/* GPIO32..63 is in GPIO Bank 2 */
 #define CONFIG_OMAP3_GPIO_3	/* GPIO64..95 is in GPIO Bank 3 */
@@ -43,13 +53,8 @@
 #define CONFIG_OMAP3_GPIO_6	/* GPIO160..191 is in GPIO Bank 6 */
 
 /* commands to include */
-#define CONFIG_CMD_CACHE
-#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
-#undef CONFIG_CMD_IMI		/* iminfo			*/
-#undef CONFIG_CMD_NFS		/* NFS support			*/
 
 #ifdef CONFIG_NAND
-#define CONFIG_CMD_UBI		/* UBI-formated MTD partition support */
 #define CONFIG_CMD_UBIFS	/* Read-only UBI volume operations */
 
 #define CONFIG_RBTREE		/* required by CONFIG_CMD_UBI */
@@ -77,7 +82,6 @@
 #endif /* CONFIG_NAND */
 
 /* Board NAND Info. */
-#define CONFIG_SYS_NAND_QUIET_TEST
 #define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
 							/* to access nand */
 /* Environment information */
@@ -94,7 +98,7 @@
 	"defaultdisplay=dvi\0" \
 	"mmcdev=0\0" \
 	"mmcroot=/dev/mmcblk0p2 rw\0" \
-	"mmcrootfstype=ext3 rootwait\0" \
+	"mmcrootfstype=ext4 rootwait\0" \
 	"nandroot=ubi0:rootfs ubi.mtd=4\0" \
 	"nandrootfstype=ubifs\0" \
 	"mtdparts=" MTDPARTS_DEFAULT "\0" \
@@ -126,6 +130,8 @@
 		"bootm ${loadaddr}\0" \
 	"loadzimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}\0" \
 	"loadfdt=load mmc ${mmcdev}:2 ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+	"loadubizimage=ubifsload ${loadaddr} ${bootdir}/${bootfile}\0" \
+	"loadubifdt=ubifsload ${fdtaddr} ${bootdir}/${fdtfile}\0" \
 	"mmcbootfdt=echo Booting with DT from mmc ...; " \
 		"run mmcargs; " \
 		"bootz ${loadaddr} - ${fdtaddr}\0" \
@@ -134,6 +140,13 @@
 		"if nand read ${loadaddr} linux; then " \
 			"bootm ${loadaddr};" \
 		"fi;\0" \
+	"nanddtsboot=echo Booting from nand with DTS...; " \
+		"run nandargs; " \
+		"ubi part rootfs; "\
+		"ubifsmount ubi0:rootfs; "\
+		"run loadubifdt; "\
+		"run loadubizimage; "\
+		"bootz ${loadaddr} - ${fdtaddr}\0" \
 
 #define CONFIG_BOOTCOMMAND \
 	"mmc dev ${mmcdev}; if mmc rescan; then " \
@@ -161,12 +174,10 @@
 		"fi;" \
 	"fi;" \
 	"run nandboot; " \
-
-/*
- * Miscellaneous configurable options
- */
-#undef CONFIG_SYS_PROMPT
-#define CONFIG_SYS_PROMPT		"Overo # "
+	"if test -z \"${fdtfile}\"; then "\
+		"setenv fdtfile omap3-${boardname}-${expansionname}.dtb;" \
+	"fi;" \
+	"run nanddtsboot; " \
 
 /* memtest works on */
 #define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
@@ -200,21 +211,25 @@
 /* Initial RAM setup */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
 #define CONFIG_SYS_INIT_RAM_SIZE	0x800
-#define CONFIG_SYS_CACHELINE_SIZE	64
 
 /* NAND boot config */
-#define CONFIG_SYS_NAND_BUSWIDTH_16BIT	16
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
+#define CONFIG_SYS_NAND_MAX_ECCPOS  56
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 #define CONFIG_SYS_NAND_PAGE_COUNT	64
 #define CONFIG_SYS_NAND_PAGE_SIZE	2048
 #define CONFIG_SYS_NAND_OOBSIZE		64
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
-#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
-						10, 11, 12, 13}
+#define CONFIG_SYS_NAND_ECCPOS      {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
+					13, 14, 16, 17, 18, 19, 20, 21, 22, \
+					23, 24, 25, 26, 27, 28, 30, 31, 32, \
+					33, 34, 35, 36, 37, 38, 39, 40, 41, \
+					42, 44, 45, 46, 47, 48, 49, 50, 51, \
+					52, 53, 54, 55, 56}
 #define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	3
-#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
+#define CONFIG_SYS_NAND_ECCBYTES	13
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
 /* NAND: SPL falcon mode configs */